Host Interface
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COM-C | Communication Module
DOC021001DG12EN | Revision 12 | English | 2011-06 | Released | Public
© Hilscher, 2002-2011
3.4.6
Interrupt Line to the Host System
The signal INT# can be used to generate an interrupt at the host system when the COM-C Module
writes into the special handshake cells of the Dual-port memory. These cells are used for synchro-
nization of the COM-C Module and the host system and have some handshake bits. For detailed
information see the special documentation for the Dual-port memory software protocol. The inter-
rupt will be only cleared if the host reads a handshake cells.
3.4.7
Busy Line to the Host System
The signal BUSY# is used to insert wait states into an current access from host system to a COM-
C module. When the signal is active the host must hold on the current transfer.
3.4.8
Interfacing to the Dual-Port Memory of COM-C
If you connect the host system to the Dual-port memory you have to know some details of the func-
tional working of the used microcontroller EC1. Generally it works like a standard SRAM. To en-
sure the proper operation of the Ethernet and the PROFIBUS when the host systems generates
very low speed accesses you have to consider the BUSY# signal.
To solve this problem, the external accesses to the EC1 Dual-port memory are internally synchro-
nized to the EC1 memory cycle. This technique actually removes the possibility of the EC1 and the
external interface accessing the Dual-port memory at the same time. The internal memory bus ar-
bitration logic insures that this cannot happen. The external interface may have to wait for several
EC1 memory cycles, but this is a short 80-145 ns compared to the 500 ns of the PC/ISA cycle.
When the PC/ISA interface starts its access to the Dual-port memory, the request is synchronized,
and the memory cycle to the Dual-port memory is completed during a normal EC1 memory cycle of
20.8 ns. The only additional requirement is that the write data has to be valid when the WR# strobe
for the external memory access becomes active. Fortunately, this is the normal case.
Note
It is not possible to switch the address line with active CE# and WR# or RD# lines (no
burst access). The internal synchronization cycle is started only when CE# and WR' or
RD# is going low.
The EC1 does have a busy signal to synchronize the external accesses to the Dual port memory.
The BUSY# signal is a normally low signal that goes high once the Dual-port memory access has
completed. It will remain high until the external cycle completes. If the external memory cycle is
longer than 145 ns, then the BUSY# signal can just be ignored.
For further details please refer the following timing diagrams.
