CIRCUIT DESCRIPTION
Refer to the Schematic (fold-in) while you read the
following “Circuit Description.” The following
paragraphs are grouped according to the various cir
cuits on the circuit board.
ADDRESS DECODER
Integrated circuits U4 and U5 form the address de
coder which decodes I/O address 362Q from the ad
dress bus. Whenever octal address 362Q appears on
the bus, the output of inverting buffer U4D (pin 8)
goes to a logic 1. NAND gates U6A and U6B AND this
362Q address signal with the IOR (read) and IOW
(write) signals to generate the read and write signals
that are exclusive to I/O address 362Q.
STATUS PORT
An octal tri-state buffer and an 8-section slide switch
form the status port. The data bus reads the switch
information from port 362Q when buffer U2 is en
abled. Address decoder U6A enables this buffer via
pins 1 and 19.
ROM DISABLE
Latch U3A and buffer U6D generate the ROM DIS
ABLE signal. If data bit D5 is low and a write is
performed at I/O address 362Q, the write signal
(362IOW) from U6B clocks the data bit into U3A and
causes its Q output to go high (logic 1). This causes
the output of U6D to go low and asserts the ROM
DISABLE signal on the bus.
SIDE SELECT
Latch U3B and buffer U6C generate the SIDE SELECT
signal. If data bit D6 is low and a write is performed at
I/O address 362Q, the write signal (362IOW) from
U6B clocks the data bit into U3B and causes its Q
output to go high (logic 1). This causes the output of
U6C to go low and asserts the SIDE SELECT signal at
plug Pl pin 2 and at circuit board hole A.
VOLTAGE REGULATOR
Integrated circuit Ul is a conventional 3-terminal vol
tage regulator which converts the unregulated 8-volts
DC available on the Computer’s bus to a regulated
5-volts DC. This regulated voltage operates all of the
integrated circuits on the Extended Configuration
Board.
