DT10 Hardware Manual
Copyright © 2012-2014 Heartland. Data Inc.
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2.5. GPIO connection 4bit / 2bit
2.5.1. Timing chart
GPIO bus timing
* In the case of “GPIO 2bit”, DAT[0:1]
No.
Description
MIN.
MAX.
UNIT
1
CS (Low) - CLK timing
20
ns
2
Data hold timing
20
ns
3
Data setup timing
20
ns
4
CLK switch period
40
ns
5
CLK - CS (High) timing
20
ns
6
CS (High) period
20
ns
・
Data is transferred as 4bit parallel and output as MSB First in order of the following items:
・
Latch timing is the edge of CLK rising and falling.
1. Argument of _TP_BusOut () dat (16bit)
2. Argument of _TP_BusOut () addr (0 - 24bit)
* In the case of 4bit, the number of “addr” bit varies (0/4/8/12/16/20/24)
and high-order bits less
than 24bit are treated as “0”.
* In the case of 2bit, the number of “addr” bit varies (0/2/4/6/8/10/12/14/16/18/20/22/24)
and
high-order bits less than 24bit are treated as “0”.
Caution
CS must be set “high”, except when outputting the Test Point.
Never set it to “low” when the Test Point output stops.
