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Rev. 1.3
15
System reference clock
The PXIe 3U 8slot series backplane supplies PXI_CLK10, PXIE_CLK100, and PXIE_SYNC100 independently
driven to each slot.
PXI_CLK10, PXIe_CLK100 and PXIe_SYNC100 have the default timing relationship according to
PXI-5 PXI
Express Hardware Specification.
The timing relations are as shown in Figure 2-6.
The 10 MHz reference clock input is derived from an internal clock oscillator.
Figure 2-7 shows the Clock architecture of the PXIe 3U 8slot series backplane.
The PLL is connected to the 10ppm 10 MHz clock oscillator. All clock outputs are synchronous to the 10 MHz
reference clock input through the oscillator.
Each of the clocks PXI_CLK10, PXIE_CLK100, and PXIE_SYNC100 are driven with independent buffers.
