Harris HSP50210EVAL, Руководство пользователя

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Item 4: Carrier Acq. Fractional Loop Bandwidth
(0.0 to 0.125)
This is the single-sided loop noise bandwidth used for acqui-
sition. Enter the bandwidth desired at the design SNR (it will
narrow as SNR decreases). Fractional loop bandwidth is the
ratio of the loop bandwidth to the baud rate (or the rate that
the loop filter is updated). For example a loop bandwidth of
1kHz at 100kbaud would have a FLBW of 0.01.
Item 5: Carrier Tracking Fractional Loop Bandwidth
(0.0 to 0.125)
This is the single-sided loop noise bandwidth used for track-
ing. Enter the bandwidth desired at the design SNR (it will
narrow as SNR decreases). Fractional loop bandwidth is the
ratio of the loop bandwidth to the baud rate (or the rate that
the loop filter is updated). For example a loop bandwidth of
1kHz at 100kbaud would have a FLBW of 0.01. The tracking
bandwidth is used during lock verification.
Item 6: Carrier Tracking Loop Damping Factor
(0.0 to 1.5)
This damping factor is used for acquisition and tracking.
Enter the damping desired at the design SNR
Item 7: Carrier AFC Function Enabled
(0; 1)
0 = Off; 1 = On
This item enables/disables the frequency error term to the
carrier loop lag accumulator during both acquisition and
tracking. To enable only during acquisition or tracking, zero
the AFC gain for the mode not wanted.
Item 8: AFC Error Gain (acquisition)
(0 to 26,000,000)
This is the gain for the frequency error term summed into the
carrier lag accumulator. This is in Hz/Hz (i.e. if constant
offset of 100Hz is measured and the gain is set to 100Hz/Hz,
the lag accumulator will move by 10,000Hz during one
second).
Item 9: AFC Error Gain (tracking)
(0 to 26,000,000)
This is the gain for the frequency error term summed into the
carrier lag accumulator. This is in Hz/Hz (i.e. if constant
offset of 100Hz is measured and the gain is set to 100Hz/Hz,
the lag accumulator will move by 10,000Hz during one
second).
Item 10: Delay in AFC Discriminator (x half baud)
(0; 1; 2; 3; 4)
0 = 1 samples; 1 = 2 samples;
2 = 4 samples; 3 = 8 samples, and 4 = 16 samples
The frequency offset is calculated by differencing the carrier
phase error after a delay (dp/dt). The delay is in half baud
intervals (for this program). Longer delays give higher gains.
Aliasing can occur in the detector if the filtering is not tight
enough for the delay chosen. The delay can be set to 1, 2, 4,
8, or 16 samples (0.5, 1, 2, 4, or 8 baud intervals).
Item 11: Acquisition Sweep Rate
(0Hz/baud to 1,000,000Hz/baud)
This is the amount that the lag accumulator is incremented
each time the loop filter runs (during swept acquisition
mode) or each time the lock detector times out (during
stepped acquisition mode).
Item 12: Carrier Tracking Bits To DQT
(0; 1; 2; 3)
0 = 8, 1 = 16, 2 = 24, and 3 = 32 bits.
This is the number of bits of the offset frequency sent from
the HSP50210 to the HSP50110. At higher data rates, fewer
bits can be used since the ratio between the clock rate and
the loop bandwidth can be lower. This allows for faster
updates and less delay around the loop.
Item 13: Carrier Tracking Mode
(0; 1; 2)
0 = lead and lag terms to DQT
1 = lead to DCL, lag to DQT
2 = lead and lag terms to DCL
These tracking modes offer a trade-off between delay around
the loop and how well the signal is kept centered in the filtering.
Mode 0 has the longest delay around the loop; mode 1 has a
shorter delay for the lead term, so wider loop bandwidths can
be used while the signal is still centered in the filtering; mode 2
has the shortest delay and uses the HSP50110 as a fixed
tuner. Mode 2 allows the widest loop bandwidths, but the carrier
offset must be small relative to the baud rate.
Item 14: DCL Slow Serial Output Clock
(2; 4; 8; 16)
If the frequency offset serial output from the HSP50210 is
routed to a destination instead of the HSP50110 (a D/A, an
NCO), the serial data can be output at a submultiple of the
master clock. The master clock/slower clock selection is
done in menu item 15. Options are Fclk/N where N = 2, 4, 8,
or 16.
Item 15: Carrier Serial Output
(0; 1)
If the frequency offset serial output from the HSP50210 is
routed to a destination other than the HSP50110 (a D/A, an
NCO), the serial data can be output at a submultiple of the
master clock. The master clock/slower clock selection is
done here, and the speed of the slower clock slow clock is
selected in menu item 14. The options are: Fclk (the master
clock) and serial clock.
Bit Sync Loop Menu
Item 1: Bit Sync Loop Upper Tracking Limit
(-26,000,000 to 26,000,000)
This is the upper limit for bit sync loop filter lag accumulator.
This sets the upper limit on symbol acquisition and tracking.
Item 2: Bit Sync Loop Lower Tracking Limit
(-26,000,000 to 26,000,000)
This is the lower limit for bit sync loop filter lag accumulator.
This sets the lower limit on symbol acquisition and tracking.
HSP50110/210EVAL