4. POWER
The CS49400 requires a 2.5V digital power supply
for the core logic and 2.5V I/O and a 2.5V analog
power supply for the internal PLL. For systems
with external memory that runs on 3.3V, a 3.3V
digital power supply is required on the VDDSD
pins along with four digital grounds on VSSSD.
There are seven digital power pins, VDD1 through
VDD7, along with seven digital grounds, VSS1
through VSS7. There is one analog power pin,
PLLVDD, and one analog ground, PLLVSS. The
recommendations given below for decoupling and
power conditioning of the CS49400 will help to
ensure reliable performance.
4.1 Decoupling
It is necessary to decouple the power supply by
placing capacitors directly between the power and
ground of the CS49400. Each pair of power/ground
pins (VDD1/VSS1, etc.) should have its own
decoupling
capacitors.
The
recommended
procedure is to place both a 0.1uF and a 1uF
capacitor as close as physically possible to each
power pin. The 0.1uF capacitor should be closest to
the part (typically 5mm or closer).
4.2 Analog Power Conditioning
In order to obtain the best performance from the
CS49400’s internal PLL, the analog power supply
PLLVDD must be as noise-free as possible. A
ferrite bead and two capacitors should be used to
filter the VDD to generate PLLVDD. This power
scheme is shown in the typical connection
diagrams.
4.3 Ground
For two layer circuit boards, care should be taken
to have sufficient ground between the DSP and
parts in which it will be interfacing (DACs, ADCs,
S/PDIF Receivers, microcontrollers, and especially
external memory). Insufficient ground can degrade
noise margins between devices resulting in data
integrity problems.
4.4 Pads
The CS49400 has two different I/O voltage levels.
All signal pins not associated with the External
SRAM/SDRAM memory interface operate from
the 2.5V supply and are 3.3V tolerant. The external
SRAM/SDRAM memory interface operates at
3.3V only. However, if the external memory
interface is not used VDDSD1-4 may be connected
to 2.5V.
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