5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
1
V
2_C
O
R
E
1V
2cl
e
a
n
UART1_TX
U
A
R
T
1_R
X
+
3
V
3
_PNX
+
3
V
3
_PNX
+
3
V
3
_PNX
+
3
V
3
_PNX
+
3
V
3
_PNX
+3
V
3
+
3
V
3
_PNX
+3
V
3
+3
V
3
+3
V
3
+3
V
3
+3
V
3
c
le
a
n
+3
V
3
+3
V
3
+3
V
3
+3
V
3
+3
V
3
+
3
V
3
_PNX
+
1
V
2
_
PNX
M
IU
_
A
D
D
R
(14)
K
(2,7
)
S
D
RAM_
ADDR(1
)
K
(2
)
M
IU
_
A
D
D
R
(15)
K
(2,7
)
S
D
RAM_
ADDR(2
)
K
(2
)
MIU_RDY
K(7
)
S
D
RAM_
ADDR(3
)
K
(2
)
SDRAM
_
D
A
T
A
(0
)
K(
2
)
S
D
RAM_
ADDR(4
)
K
(2
)
M
IU
_
A
D
D
R
(16)
K
(2,7
)
RESET
_
F
E
_
n
K(6
)
M
IU
_
ADDR(0
)
K(2
,7
)
S
D
RAM_
ADDR(5
)
K
(2
)
PNX_
TDI
T
S
_
D
A
TA(0)
K(7
)
STV_
A2
5
K(
7
)
N
O
R_
CS
K(2
)
PNX_
T
D
O
S
D
RAM_
ADDR(6
)
K
(2
)
NOR
_
W
P
K(2
)
TXD0
K(4
)
MI
U_
D
A
T
A
(1
)
K(2
,7
)
T
S
_
D
A
TA(1)
K(7
)
S
D
RAM_
ADDR(7
)
K
(2
)
PNX_
T
D
O
S
D
RAM_
ADDR(8
)
K
(2
)
SDRAM
_
D
A
T
A
(1
)
K(
2
)
T
S
_
D
A
TA(2)
K(7
)
T
S
_
D
A
TA(3)
K(7
)
T
S
_
D
A
TA(4)
K(7
)
MI
U_
D
A
T
A
(2
)
K(2
,7
)
T
S
_
D
A
TA(5)
K(7
)
M
IU
_
A
D
D
R
(17)
K
(2,7
)
T
S
_
D
A
TA(6)
K(7
)
T
S
_
D
A
TA(7)
K(7
)
S
D
RAM_
ADDR(9
)
K
(2
)
STV_
INT
K(
7
)
RESET
_STV
K(
7
)
MI
U_
D
A
T
A
(3
)
K(2
,7
)
S
D
RAM_
ADDR(1
0
)
K(
2
)
M
IU
_
A
D
D
R
(18)
K
(2,7
)
ST
V
_
C
S
K(7
)
S
D
RAM_
ADDR(1
1
)
K(
2
)
MI
U_
D
A
T
A
(4
)
K(2
,7
)
TS_
S
Y
N
C
K
(7
)
M
IU
_
A
D
D
R
(19)
K
(2,7
)
S
D
RAM_
ADDR(1
2
)
K(
2
)
MI
U_
D
A
T
A
(5
)
K(2
,7
)
SDRAM
_
D
A
T
A
(2
)
K(
2
)
M
IU
_
A
D
D
R
(20)
K
(2,7
)
S
D
RAM_
ADDR(1
3
)
K(
2
)
T
S
_C
LK
K
(7)
Y_
CVBS
P
N
X
_TMS
SDRAM
_
D
A
T
A
(3
)
K(
2
)
MI
U_
D
A
T
A
(6
)
K(2
,7
)
user
_E
E
P
R
O
M
_
W
P
K(2
)
M
IU
_
ADDR(1
)
K(2
,7
)
M
IU
_
A
D
D
R
(21)
K
(2,7
)
S
D
RAM_
ADDR(1
4
)
K(
2
)
SDRAM
_
D
A
T
A
(4
)
K(
2
)
MI
U_
D
A
T
A
(7
)
K(2
,7
)
T
S
_V
AL
ID
K(7
)
M
IU
_
A
D
D
R
(22)
K
(2,7
)
SDRAM
_
D
A
T
A
(5
)
K(
2
)
MI
U_
D
A
T
A
(8
)
K(2
,7
)
R
E
SET_
n
K(2
,3
)
MI
U
_
O
E
N
K(2
,7
)
MI
U_
WE
N
K(2
,7
)
M
IU
_
A
D
D
R
(23)
K
(2,7
)
PNX_TRST
SDRAM
_
D
A
T
A
(6
)
K(
2
)
I2
C_
TV_
SC
L
K(5
)
I2
C_
TV_
SD
A
K(5
)
MI
U_
D
A
T
A
(9
)
K(2
,7
)
SDRAM_
D
Q
M
0
K
(2
)
SDRAM
_
D
A
T
A
(7
)
K(
2
)
M
IU
_
A
D
D
R
(24)
K
(2,7
)
M
IU
_
D
A
T
A
(10)
K(2
,7
)
SDRAM
_
D
A
T
A
(8
)
K(
2
)
M
IU
_
ADDR(2
)
K(2
,7
)
SDRAM_
D
Q
M
1
K
(2
)
SDRAM
_
D
A
T
A
(9
)
K(
2
)
P
N
X
_TCK
M
IU
_
D
A
T
A
(11)
K(2
,7
)
M
IU
_
ADDR(3
)
K(2
,7
)
SDRAM_
CAS
K
(2
)
S
D
R
A
M
_D
A
T
A
(10)
K(
2
)
M
IU
_
D
A
T
A
(12)
K(2
,7
)
M
IU
_
ADDR(4
)
K(2
,7
)
RXD
0
K(4
)
PNX_
I2
S
_
O
U
T
_
S
D
K(5
)
S
D
R
A
M
_D
A
T
A
(11)
K(
2
)
SDRAM_
RAS
K
(2
)
M
IU
_
D
A
T
A
(13)
K(2
,7
)
M
IU
_
ADDR(5
)
K(2
,7
)
S
D
R
A
M
_D
A
T
A
(12)
K(
2
)
SD
R
A
M
_
W
E
K
(2
)
4
M
H
z_PNX
K(6
)
FE_L
O
C
K
K(
6
)
M
IU
_
D
A
T
A
(14)
K(2
,7
)
M
IU
_
ADDR(6
)
K(2
,7
)
S
D
R
A
M
_D
A
T
A
(13)
K(
2
)
SDRAM_
CKE
K
(2
)
TV_
IR
Q
K
(5
)
S
D
R
A
M
_D
A
T
A
(14)
K(
2
)
M
IU
_
D
A
T
A
(15)
K(2
,7
)
S
DRAM_
CL
K
K
(2
)
M
IU
_
ADDR(7
)
K(2
,7
)
NOR_RYBY
K(
2
)
S
D
R
A
M
_D
A
T
A
(15)
K(
2
)
S
D
RAM_
ADDR(0
)
K
(2
)
M
IU
_
ADDR(8
)
K(2
,7
)
I2
C
_
LO
C
A
L_S
C
L
K
(2,
6,
7
)
I2
C
_LO
C
A
L_S
D
A
K
(2,
6,
7
)
M
IU
_
ADDR(9
)
K(2
,7
)
PNX_
I2
S
_
O
U
T
_
S
C
K
K(5
)
PNX_
I2
S
_
O
U
T
_
W
S
K(5
)
SP
D
IF
K(4
)
FSC
L
K
K(5
)
B/
C
b
G/Y
R/Cr
PNX_
T
C
K
M
IU
_
A
D
D
R
(10)
K
(2,7
)
PNX_TMS
R
ESET_
n
K(2
,3
)
M
IU
_
A
D
D
R
(11)
K
(2,7
)
PNX_
TDI
MI
U_
D
A
T
A
(0
)
K(2
,7
)
M
IU
_
A
D
D
R
(12)
K
(2,7
)
PNX_TRST
M
IU
_
A
D
D
R
(13)
K
(2,7
)
GND
K
(5
)
SW
DE
BUGGING
ONLY
NC
NC
NC
D
T
V
M
O
D
U
L
E
-P
N
X831x
R3
1
3
3
R
Q2
2N
70
0
Z
3
1
22
FB4
P
B
Y
32_19 O
H
M
C
1
8
100n
C
2
3
100n
C
2
2
10u
/1
6
v
R3
10
K
R4
0
1
0
0
R
R2
1
10K
R5
10K
/N
C
C
1
5
100n
T
S
U1
-2
P
N
X
831x
TS_DATA0
20
TS_DATA1
21
TS_DATA2
22
TS_DATA3
23
TS_DATA4
24
TS_DATA5
25
TS_DATA6
26
TS_DATA7
27
TS_SYNC
30
TS_STROBE
29
TS_VAL
28
R2
6
2
2
R
R1
0
10K
(
S
DRAM)
U1
-4
PNX8
3
1
x
SDRAM_DATA0
113
SDRAM_DATA1
114
SDRAM_DATA2
115
SDRAM_DATA3
116
SDRAM_DATA4
117
SDRAM_DATA5
118
SDRAM_DATA6
121
SDRAM_DATA7
122
SDRAM_DATA8
132
SDRAM_DATA9
129
SDRAM_DATA10
128
SDRAM_DATA11
127
SDRAM_DATA12
126
SDRAM_DATA13
125
SDRAM_DATA14
124
SDRAM_DATA15
123
SDRAM_ADDR0
153
SDRAM_ADDR1
154
SDRAM_ADDR2
155
SDRAM_ADDR3
156
SDRAM_ADDR4
149
SDRAM_ADDR5
148
SDRAM_ADDR6
147
SDRAM_ADDR7
146
SDRAM_ADDR8
145
SDRAM_ADDR9
144
SDRAM_ADDR10
152
SDRAM_ADDR11
143
SDRAM_ADDR12
142
SDRAM_ADDR13
150
SDRAM_ADDR14
151
DQM0
138
DQM1
133
VAS
140
RAS
141
WE
139
CKE
137
HSCKB
136
R2
4
10
K
C
1
3
100n
R2
3
10K
R4
4
3
3
R
R2
10K
R2
9
3
3
R
C
6
100n
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
C3
1
0
u
R2
2
10K
R3
8
3
3
R
Q1
2N
70
0
Z
3
1
22
R2
5
2
2
R
R1
7
1
0
K
R1
5
10
K
R1
3
3
3
R
C
9
100n
R9
10
K
R2
8
2
2
R
(JTAG-
ETAG-SYS)
D
S
U
_TPC0
U1
-8
P
N
X
831x
YDI
208
TDO
207
TMS
1
TRST
2
TCK
3
RESETN
4
XTAL_IN
158
XTAL_OUT
159
AVDD_PLL
157
AVSS_PLL
160
SYS_RESETN
5
PCST00
194
PCST01
189
PCST02
188
PCST10
197
PCST11
196
PCST12
195
DSU_TPC1
187
DSU_CLK
186
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
C1
4
0
22
p
F
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
R1
8
1
0
K
R1
1
33
R
R4
2
3
3
R
C
1
6
100n
C4
1
0
u
R
53-
N
C
10K
_
N
C
R1
6
1
0
K
R7
10
K
C
5
100n
C2
10u
R4
3
1
0
0
R
C
2
1
100n
R5
4
1K
2
R
530-
N
C
0
R
_nc
J2
B2
B-
P
H
-K
1
2
R4
33
R3
2
3
3
R
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
R5
2
10
K
C
1
41
2
2
pF
C
1
2
100n
R1
4
3
3
R
C
8
100n
C
2
5
10u
/1
6
v
FB2
1
00M
H
Z
R6
68R
/N
C
VS
P
L
L
_OUTX0
VCXO
_CLOCK
(
G
PIO)
U1
-7
P
N
X
831x
IR_IN
31
IR_OUT
32
PWM
185
VPP
33
C4
34
C8
35
SC1_DA
45
SC1_CMDVCC
46
SC1_RST
47
SC1_OFF
48
SC1_CCK
49
CTS0
12
RTS0
13
RX0
14
TX0
15
DCD0
16
DTR0
17
RX1
18
TX1
19
ITU_OUT0
176
ITU_OUT1
177
ITU_OUT2
178
ITU_OUT3
179
ITU_OUT4
180
ITU_OUT5
181
ITU_OUT6
182
ITU_OUT7
183
ITU_CLOCK
184
R3
5
3
3
R
FB3
1
00M
H
Z
J1
FT
S
H
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
C
1
4
100n
R1
9
1
0
K
R4
7
3
3
R
R3
7
3
3
R
C7
1
0
u
R4
6
3
3
R
(
AV)
U1
-3
PNX8
3
1
x
SD_OUT
202
SCK_OUT
203
WS_OUT
204
SPDIF
206
FSCLK
205
CVBS_Y
168
CVBS_C
172
CVBS_Y1
170
B
163
G_Y
165
R_C
167
C
2
0
100n
R4
9
1
0
0
R
C
1
7
100n
R3
3
3
3
R
R4
5
3
3
R
R3
6
3
3
R
C
1
9
100n
R2
7
2
2
R
FB1
1
00M
H
Z
R2
0
3
3
R
C
1
1
100n
C1
100p/
N
C
(
M
IU)
U1
-5
P
N
X
831x
MIU_DATA0
69
MIU_DATA1
67
MIU_DATA2
65
MIU_DATA3
63
MIU_DATA4
59
MIU_DATA5
57
MIU_DATA6
55
MIU_DATA7
53
MIU_DATA8
68
MIU_DATA9
66
MIU_DATA10
64
MIU_DATA11
62
MIU_DATA12
58
MIU_DATA13
56
MIU_DATA14
54
MIU_DATA15
52
MIU_ADDR0
75
MIU_ADDR1
80
MIU_ADDR2
81
MIU_ADDR3
82
MIU_ADDR4
83
MIU_ADDR5
84
MIU_ADDR6
85
MIU_ADDR7
86
MIU_ADDR8
87
MIU_ADDR9
88
MIU_ADDR10
89
MIU_ADDR11
90
MIU_ADDR12
91
MIU_ADDR13
92
MIU_ADDR14
93
MIU_ADDR15
96
MIU_ADDR16
97
MIU_ADDR17
98
MIU_ADDR18
99
MIU_ADDR19
100
MIU_ADDR20
101
MIU_ADDR21
102
MIU_ADDR22
103
MIU_ADDR23
104
MIU_ADDR24
105
MIU_RDY
109
MIU_CS_N0
74
MIU_CS_N1
73
MIU_CS_N2
72
MIU_CS_N3
71
MIU_OE_N
70
MIU_WEN
108
MIU_MASK0
106
MIU_MASK1
107
MIU_LBA
110
MIU_BAA
50
MIU_CLK
51
R
5
1
1
0/NC
R3
9
3
3
R
Y1
4MHz
I2C-
USB-SCO
U1
-6
P
N
X
831x
SCL0
6
SDA0
7
SCL1
8
SDA1
9
SC0_DA
36
USB_OVRCUR
198
SC0_OFF
39
SC0_CMDVCC
37
USB_PWR
199
USB_DP
200
USB_DM
201
SC0_CCK
40
SC0_RST
38
R5
3
1
0
R
_nc
R5
1
10K
C
2
4
10u
/1
6
v
R1
2
3
3
R
R3
0
2
2
R
R3
4
3
3
R
PW
R
U1
-1
PNX
8
3
1
x
VDDC
41
VDDC3
134
VDDC1
78
VDDC4
191
VDDC2
119
VDDP1
10
VDDP2
43
VDDP3
60
VDDP4
76
VDDP5
94
VDDP6
111
VDDP7
130
VDDP8
161
VDDP9
190
VSSC
42
VSSC1
79
VSSC2
120
VSSC3
135
VSSC4
192
VSSP
11
VSSP1
44
VSSP2
61
VSSP3
77
VSSP4
95
VSSP5
112
VSSP6
131
VSSP7
162
VSSP8
193
AVDD0
175
AVDD1
169
AVDD2
164
IDUMP1
171
IDUMP2
166
N1
174
N2
173
R1
10K
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
R4
8
-N
C
10K
_
N
C
R8
10
K
R4
1
3
3
R
R5
0
1
0
0
R
C
1
0
100n
Содержание 1E03-37GT
Страница 1: ...Liquid Crystal Display Television GT02 32E1 GT03 37E1 SERVICE MANUAL...
Страница 24: ...20 Exploded view 32...
Страница 25: ...21...
Страница 26: ...22 37...
Страница 27: ...23...
Страница 28: ...24 Power circuit board Printed circuit board Bottom View Top View 32 37 32 37...
Страница 29: ...25 Main Board Top View Bottom View...
Страница 30: ...26...
Страница 31: ...27...
Страница 32: ...28...
Страница 61: ......