Grimm Audio CC1, Руководство пользователя

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but as far as signal quality is concerned you’re better off with a stable clock at an
inexact frequency.
Jitter is not a problem in fully digital processes. As long as it isn’t so large that a
processor can’t distinguish the previous bit from the next, all-digital processes are
completely indifferent about jitter. The problem occurs when you go from the ana-
logue domain into the digital domain or back. Digital audio presumes uniform sam-
pling. That way, given a string of numbers and knowledge of the sampling interval,
you can perfectly reconstruct a sampled signal. With jitter that theory falls flat on its
back.
Imagine the signal on top. The AD converter samples it at neatly uniform intervals.
The DA converter reconstructs the correct values but it gets the timing wrong. The
difference between the red and blue curve shows the error. Or take the converse:
the DAC is fine but the ADC took samples at the wrong time. The effect is much the
same. What’s worse in this case is that the numbers we’ve recorded are now wrong.
In the previous case we could slap in a better DAC, with a jittery ADC the game is
over.
PLL’s
Converter chips need a high frequency clock signal, usually something around
22MHz. It is always made by a local oscillator (anything from a simple RC oscillator
in a receiver chip to a crystal oscillator) regardless of whether the unit is operating
in master or slave mode. This local oscillator is indispensible: external sync sig-
nals may be AES/EBU, a sample rate frequency “word clock” or even a video signal,
neither of which are of any direct use to the AD/DA. Instead, the local oscillator is
sped up or slowed down to make it run in step with (“locked to”) the sync signal. A
system that uses a local oscillator “pulled” in sync with an external signal is called
a Phase Locked Loop (PLL). A “phase detector” compares the local clock with the
Jitter in AD (top) and DA (bottom) converters