2 Overview
2.5 Pin Definitions
UG884-1.01E
7(14)
Pin Name
I/O
Description
SI /D2
I/O
MISO in MSPI mode: Master data output/Slave data
input
Data port D2 in CPU mode
TMS
I, internal weak
pull-up
Serial mode input in JTAG mode
TCK
I
Serial clock input in JTAG mode, which needs to be
connected with 4.7 K drop-down resistance on PCB
TDI
I, internal weak
pull-up
Serial data input in JTAG mode
TDO
O
Serial data output in JTAG mode
JTAGSEL_N
I, internal weak
pull-up
Select signal in JTAG mode, active-low
SCLK
I
Clock input in SSPI, SERIAL, and CPU mode
DIN
I, internal weak
pull-up
Input data in SERIAL mode
DOUT
O
Output data in SERIAL mode
CLKHOLD_N
I, internal weak
pull-up
High level, SCLK will be connected internally in SSPI
mode or CPU mode
Low level, SCLK will be disconnected from SSPI
mode or CPU mode
WE_N
I
Select data input/output of D[7:0] in CPU mode
GCLKT_[x]
I
Pins in global clock input, T(True), [x]: global clock
No.
GCLKC_[x]
I
Pins for Global clock input, C(Comp), [x]: global
clock No.
LPLL_T_fb/RPLL_T_fb
I
L/R PLL feedback input pin, T(True)
LPLL_C_fb/RPLL_C_fb I
L/R PLL feedback input pin, C(Comp)
LPLL_T_in/RPLL_T_in
I
L/R PLL clock input pin, T(True)
LPLL_C_in/RPLL_C_in
I
L/R PLL clock input pin, C(Comp)
CH[7:0]
I
Eight-channel analog input
MODE2
I, internal weak
pull-up
GowinCONFIG modes selection pin; if this pin is not
bonded, it's internal grounded.
MODE1
I, internal weak
pull-up
GowinCONFIG modes selection pin; if this pin is not
bonded, it's internal grounded.
MODE0
I, internal weak
pull-up
GowinCONFIG modes selection pin; if this pin is not
bonded, it's internal grounded.
Other Pins
NC
NA
Reserved.
VSS
NA
Ground pins
VCC
NA
Power supply pins for internal core logic.
VCCO#
NA
Power supply pins for the I/O voltage of I/O BANK#.
VCCX
NA
Power supply pins for auxiliary voltage.
VCCP
NA
FLASH Power supply pin (1.8V)
VCCPLL
NA
Power supply pins in PLL
USB Power supply pin
DM
NA
USB data pin Data-
DP
NA
USB data pin Data+
Содержание GW1NSER Series
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