GOWIN GW1NSER Series, Руководство пользователя

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2 Overview 2.5 Pin Definitions
UG884-1.01E 6(14)
2.5 Pin Definitions
The location of the pins in the GW1NSER series of SecureFPGA
products varies according to the different packages.
Table 2-4 provides a detailed overview of user I/O, multi-function pins,
dedicated pins, and other pins.
Table 2-4 Definition of the Pins in the GW1NSER series of SecureFPGA products
Pin Name I/O Description
Max. User I/O
IO[End][Row/Column
Number][A/B]
I/O
[End] indicates the pin location, including L(left)
R(right) B(bottom), and T(top)
[Row/Column Number] indicates the pin
Row/Column number.If [End] is T(top) or B(bottom),
the pin indicates the column number of the
corresponding CFU. If [End] is L(left) or R(right), the
pin indicates the Row number of the corresponding
CFU.
[A/B] indicates differential signal pair information.
Multi-Function Pins
IO[End][Row/Column Number][A/B]/MMM
/MMM represents one or more of the other functions
in addition to being general purpose user I/O. These
pins can be used as user I/O when the functions are
not used.
RECONFIG_N
I, internal weak
pull-up
Start new GowinCONFIG mode when low pulse
READY I/O
When high level, the device can be programmed and
configured
When low level, the device cannot be programmed
and configured
DONE I/O
High level indicates successful program and
configure
Low level indicates incomplete or failed to program
and configure
FASTRD_N /D3 I/O
In MSPI mode, FASTRD_N is used as Flash access
speed port. Low indicates high-speed Flash access
mode; high indicates regular Flash access mode.
Data port D3 in CPU mode
MCLK /D4 I/O
Clock output MCLK in MSPI mode
Data port D4 in CPU mode
MCS_N /D5 I/O
Enable signal MCS_N in MSPI mode, active-low
Data port D5 in CPU mode
MI /D7 I/O
MISO in MSPI mode: Master data input/Slave data
output
Data port D7 in CPU mode
MO /D6 I/O
MISO in MSPI mode: Master data output/Slave data
input
Data port D6 in CPU mode
SSPI_CS_N/D0 I/O
Enable signal SSPI_CS_N in SSPI mod, active-low,
Internal Weak Pull Up
Data port D0 in CPU mode
SO /D1 I/O
MISO in MSPI mode: Master data input/Slave data
output
Data port D1 in CPU mode