3 Development Board Circuit
3.8 Camera
DBUG391-1.0E
16(20)
Name
Pin No.
BANK
I/O Level
Description
HDMI_TXA1P
32
2
2.5V
HDMI differential data
HDMI_TXA1N
31
2
2.5V
HDMI differential data
HDMI_TXA0P
30
2
2.5V
HDMI differential data
HDMI_TXA0N
29
2
2.5V
HDMI differential data
HDMI_TXACP
28
2
2.5V
HDMI differential
clock
HDMI_TXACN
27
2
2.5V
HDMI differential
clock
3.8
Camera
3.8.1
Overview
The camera interface is connected directly to the 24pin FPGA pin FPC
connector with 0.5mm pitch, and the signal is received/transmitted through
the internal IP of FPGA.
3.8.2
FPC Interface
Figure 3-6 FPC Interface Connection Circuit
FH12_24S_0.
5SH
U1
J5
GW2AR-
LV18QN88P
PIXDATA3
PIXDATA4
PIXDATA5
PIXDATA6
PIXDATA7
PIXDATA8
PIXDATA9
HREF
VSYNC
SCL
19
20
18
16
23
40
42
43
44
39
PIXDATA2
PIXDATA1
PIXDATA0
17
21
22
SDA
PIXCLK
XCLK
46
41
33
GW1NSR4
Содержание DK_GoAI_GW1NSR-LV4CQN48PC7I6
Страница 1: ...DK_GoAI_GW1NSR LV4CQN48PC7I6_V2 2 User Guide DBUG391 1 0E 03 03 2021 ...
Страница 3: ...Revision History Date Version Description 03 03 2021 1 0E Initial version published ...
Страница 27: ...5 Gowin Software DBUG391 1 0E 20 20 5 Gowin Software See SUG100 Gowin Software User Guide for details ...
Страница 28: ......