GW1NS & GW1NSR & GW1NSE & GW1NSER Series of FPGA
Products Schematic Manual
UG292-1.0E
www.gowinsemi.com.en
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MSPI
Overview
FPGA as a master device, MSPI reads the data automatically from the
off-chip flash then transmits it to the FPGA SRAM.
Signal Description
Table 3 Signal Description
Name
I/O
Description
MCLK
O
Clock output in MSPI mode
MCS_N
O
MCS_N in MSPI mode, low-active
MI
I
Data input in MSPI mode
MO
O
Data output in MSPI mode
MSPI Circuit Reference
Figure 3 MSPI Circuit Reference
CS
WP
DO
GND
VCC
HOLD
CLK
DI
1
2
3
4
5
6
7
8
MCS_N
MI
R
VCC3P3
4.7K
MCLK
MO
SPI FLASH
U
R
4.7K
C
100nF
VCC3P3
R
1K
Note!
MCLK signal requires 1K pull-down resistor.
The resistance accuracy is not less than ± 5%.
Clock Pins
Overview
The clock pins include GCLK global clock pins and PLL clock pins.
GCLK: GCLK in FPGA products distributes in L and R quadrants. Each
quadrant provides eight GCLK nets. The clock source of each GCLK
can be dedicated pin or CRU, and the dedicated pin can provide better
performance.
PLL: Frequency (multiplication and division), phase, and duty cycle can
be adjusted by configuring the parameters.