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GOWIN DK START GW1NS-LV4CQN48C7I6 V1.1, Схематическое руководство, Страница: 14 / 16

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GW1NS & GW1NSR & GW1NSE & GW1NSER Series of FPGA 
Products Schematic Manual 
UG292-1.0E

 

 

 

www.gowinsemi.com.en 

14

(

15

) 

 

Pinout 

Before the design of the circuit, you should take the FPGA pinout into 

consideration, and a reasonable choice should be made for IO LOGIC, 
global clock resource, PLL and differential signals, etc. 

Note! 

During the configuration, all I/O (except TCK) of the device is weak pull-up, and I/O status 
after configuration is controlled by user programs and constraints. 

Содержание DK START GW1NS-LV4CQN48C7I6 V1.1

Страница 1: ...istics of GW1NS GW1NSR GW1NSE GW1NSER series of FPGA products The main contents of this manual are as follows Power Supply JTAG MSPI Clock Pin Difference Pin READY RECONFIG_N DONE MODE JTAGSEL_N FASTRD_N Configure Dual purpose Pin External Crystal Oscillator Circuit Reference Bank Voltage Configuration Modes Supported by Each Device MIPI ADC USB Pinout Power Supply Overview GW1NS GW1NSR GW1NSE GW1...

Страница 2: ... 5V and 3 3V After the chip powers on VCCX can be turned off VCCO Bank can be set to 1 2V 1 5V 1 8V 2 5V or 3 3V as required Power Index The device can only operate when the power voltage is in the recommended range Table 1 lists the recommended range Table 1 Recommended Range Name Description Min Max VCC Core voltage 1 14V 1 26V VCCOx I O Bank voltage for LX version 1 14V 1 89V I O Bank voltage f...

Страница 3: ...oading the bitstream to SRAM on chip flash or off chip flash of FPGA Signal Description Table 2 Signal Description Name I O Description TCK I JTAG serial clock input TMS I internal weak pull up JTAG serial mode input TDI I internal weak pull up JTAG serial data input TDO O JTAG serial data output JTAG Circuit Reference Figure 2 JTAG Circuit Reference R 4 7K TCK R R R R 22 22 22 22 VCC3P3 TDI TDO T...

Страница 4: ...eference Figure 3 MSPI Circuit Reference CS WP DO GND VCC HOLD CLK DI 1 2 3 4 5 6 7 8 MCS_N MI R VCC3P3 4 7K MCLK MO SPI FLASH U R 4 7K C 100nF VCC3P3 R 1K Note MCLK signal requires 1K pull down resistor The resistance accuracy is not less than 5 Clock Pins Overview The clock pins include GCLK global clock pins and PLL clock pins GCLK GCLK in FPGA products distributes in L and R quadrants Each qua...

Страница 5: ...om PLL_T GCLK is the global clock and is connected to all resources in the device It is recommended to input from GCLK_T Differential Pins Overview Differential transmission is a kind of signal transmission which is different from the traditional signal line and ground line Differential transmission signals are transmitted on these two lines These two signals are with same amplitudeAmplitude phase...

Страница 6: ...the device to reconfigure as required You can configure FPGA only when the READY signal is high The device should be restored by power on or triggering RECONFIG_N when the READY signal is low As an output configuration pin it can indicate whether the FPGA can be configured currently If the device is ready READY signal is high If the device fails to configure the READY signal changes to low As an i...

Страница 7: ...ation uncompleted or failed READY RECONFIG_N DONE Reference Circuit Figure 4 READY RECONFIG_N DONE Reference Circuit READY DONE RECONFIG_N R 4 7K R 4 7K R 4 7K D VCC3P3 Note The pull up power supply is the bank voltage value VCCO0 of the corresponding pin The resistance accuracy is not less than 5 MODE Overview MODE includes MODE0 MODE1 MODE2 and GowinCONFIG When FPGA powers on or a low pulse trig...

Страница 8: ...er FPGA reads data from external Flash or other devices via the SPI interface for configuration DUAL BOOT 110 FPGA reads data from external Flash first and if the external Flash fails it reads from the internal Flash SERIAL 101 External Host configure FPGA products of LittleBee Family via DIN interface CPU 111 External Host configure FPGA products of LittleBee Family via DBUS interface JTAGSEL_N O...

Страница 9: ...se refer to the corresponding Flash datasheet Signal Description Table 10 Signal Description Pin Name I O Description FASTRD_N I O As a configuration pin internal weak pull up READY signal rising edge samples MSPI configuration speed mode As a GPIO it can be used as input or output Note High level Normal Flash mode clock frequency should not be higher than 30MHz Low level High speed Flash mode clo...

Страница 10: ...input or output If DONE is used as an input GPIO the initial value of DONE should be 1 Otherwise the FPGA will fail to enter the user mode after configuring As a GPIO JTAG can be used as an input or output As a GPIO JTAGSEL_N can be used as an input or output As a GPIO JTAG can be used as an input or output You multiplex MODE pin the correct value is needed to provided during configuration power o...

Страница 11: ...is not less than 5 and capacitance accuracy is not less than 20 Bank Voltage For the Bank power supply requirements of the devices please refer to the Power section of the following documents UG825 GW1NS 2C Pinout UG822 GW1NS 2 Pinout UG824 GW1NS 4 4C Pinout UG862 GW1NSR 2 2C Pinout UG864 GW1NSR 4 Pinout UG865 GW1NSR 4C Pinout UG872 GW1NSE 2C Pinout UG883 GW1NSER 4C Pinout Configuration Modes Supp...

Страница 12: ...49 QN48 MG64 GW1NSR 2 2C Table 14 GW1NSR 2 2 C Configuration Modes Configuration Modes JTAG AUTO BOOT QN48 GW1NSE 2C Table 15 GW1NSE 2 C Configuration Modes Configuration Modes JTAG AUTO BOOT QN48 LQ144 GW1NSER 4C Table 16 GW1NSER 4 C Configuration Modes Configuration Modes JTAG AUTO BOOT QN48G QN48P GW1NSR 4C Table 17 GW1NSR 4 C Configuration Modes Configuration Modes JTAG AUTO BOOT MG64P MIPI GW...

Страница 13: ...erformance Slew Rate Max 1MHz Dynamic range 81 dB SFDR 62 db SINAD Linear performance INL 1 LSB DNL 0 5 LSB no missing codes ADC Reference Voltage The reference voltage can be enabled or disabled by configuring parameters VREF_EN 1 enabled VREF_EN 0 disabled and Vref is provided by Vccx When Vref is enabled there are two ways to provide Vref internal and external The internal is provided by Vccx a...

Страница 14: ...of the circuit you should take the FPGA pinout into consideration and a reasonable choice should be made for IO LOGIC global clock resource PLL and differential signals etc Note During the configuration all I O except TCK of the device is weak pull up and I O status after configuration is controlled by user programs and constraints ...

Страница 15: ...k Gowin Semiconductor provides customers with comprehensive technical support If you have any questions comments or suggestions please feel free to contact us directly by the following ways Website www gowinsemi com E mail support gowinsemi com Revision History Date Version Description 07 28 2020 1 0 Initial version published ...

Страница 16: ... identified as trademarks or service marks are the property of their respective holders as described at www gowinsemi com GOWINSEMI assumes no liability and provides no warranty either expressed or implied and is not responsible for any damage incurred to your hardware software data or property resulting from usage of the materials or intellectual property except as outlined in the GOWINSEMI Terms...

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