Goodmans GPS160MPT, Руководство по обслуживанию

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MIC2
GND
MIC1
SCHEMATIC DIAGRAM
REF:D:/ORCAD/NGAILIK/MPEGBOARD:CA711.SCH
R
D
7
R
A
0
D
A
1
D
A
3
D
A
6
D
A
5
D
A
4
D
A
8
D
D
8
D
D
1
2
R
D
3
R
D
4
R
D
2
R
D
1
R
D
5
R
D
6
R
D
0
R
A
1
R
A
2
R
A
3
R
A
1
0
R
A
4
R
A
1
1
R
A
5
RA16
RA17
RA15
RA14
RA12
RA13
RA7
RA6
RA9
D
A
2
D
A
0
D
A
7
DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD15
DD14
DD13
DA10
DA9
D
D
1
1
D
D
1
0
D
D
9
/W
E
/C
A
S
/R
A
S
0
DQM0
BA0
VSYNC
HSYNC
EXT_CLK
CL_SW
A
U
_
X
C
K
A
U
_
D
A
T
A
A
U
_
L
R
C
K
A
U
_
B
L
C
K
V
ID
_
P
/N
T
V
R
E
S
PAD1
PAD0
SQSO
RA8
C
D
_
B
L
C
K
C
D
_
L
R
C
K
C
D
_
D
A
T
A
IR
I
S
Q
C
K
V
F
D
_
C
L
K
V
F
D
_
D
A
T
A
V
F
D
_
S
T
B
X
R
S
T
C
L
O
S
E
O
P
E
N
D
D
A
T
X
L
A
T
C
L
O
K
S
C
O
R
L
D
O
N
S
H
O
C
K
M_RESET
SDRAM_CLK
27MHZ
HSYNC
VSYNC
VID_P/N
YC3
YC7
YC4
YC5
YC0
YC2
YC6
YC1
SDRAM_CLK
BA0
/RAS0
/CAS
/WE
DQM0
S
E
N
S
CD_DATA
CD_LRCK
CD_BLCK
AU_LRCK
SQSO
CLOSE
SQCK
CLOK
XLAT
OPEN
SCOR
LDON
2SPEED
CL_SW
AUD_MUTE
PAD0
PAD1
IRI
SENS
AU_DATA
AU_BLCK
PLLVCC25
XRST
AUD_MUTE
ADDR18
RA18
2SPEED
C2PO SHOCK
AU_XCK
VFD_STB
VFD_CLK
DDAT
VFD_DATA
TVRES
C
D
R
W
2
7
M
H
Z
CDRW
EXT_CLK
27MHZ
HSYNC
VSYNC
VID_P/N
YC[0..7]
RA[0..18]
RD[0..7]
DA[0..10]
DD[0..15]
SDRAM_CLK
BA0
/RAS0
/CAS
/WE
DQM0
AU_XCK
AU_DATA
AU_LRCK
SQCK
SQSO
XRST
XLAT
CLOK
DDAT
SCOR
RW.SW
CL_SW
VFD_STB
VFD_CLK
SENS
AU_BLCK
C2PO
DISP_RS
KEY5
AUD_MUTE
KEY1
DBSP
IR_IN
DISP_E
KEY2
KEY4
SCLK
EXT_CLK
EXT_DAT
VFD_DATA
TVRES
KEY3
CD_DATA
CD_LRCK
CD_BCLK
KEY2
KEY1
KEY3
KEY4
KEY5
GND
VCC
G
N
D
G
N
D
V
C
C
2
5
GND
VCC
VCC3
GND
VCC25
G
N
D
G
N
D
G
N
D
MICVCC
G
N
D
V
C
C
3
VCC25
V
C
C
2
5
V
C
C
3
G
N
D
MICGND
DRVCC
GND
VCC25
MICGND
MICGND
GND
GND
GND
GND
VCC25
GND
MICGND
V
C
C
3
V
C
C
3
GND
GND
VCC
+
TC6
10U
C14
22P
R127
10K
+
TC4 10U
BC8
0.1U
R124
10K
CN4
MIC
1
2
3
R23 330
R21 10K
R16 24K
R20 10K
R28 0
Q5
9014 2
1
3
R125
10K
R18
1K
C11
0.068U
+
TC3
10U
BC3
0.1U
+
TC5 10U
C10
500P
R22 10K
BC6
0.1U
R14
10K
R24
OPEN
R126
10K
BC2
0.1U
U2
SPCA718-128
3
8
3
7
3
6
39
43
41
42
40
44
48
47
45
49
50
51
55
54
53
52
56
57
58
59
8
1
7
9
7
8
7
7
7
6
7
5
7
4
7
3
7
2
7
1
7
0
6
9
6
8
6
7
6
6
6
5
64
63
62
61
60
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
3
0
3
2
3
4
3
5
7 8 9 1
0
1
1
3 4 5 6
105
106
9
8
108
1
0
0
110
111
112
113
114
115
118
128
122
9
7
9
9
1
0
1
1
0
2
103
8
5
8
4
8
3
8
2
8
0
8
8
8
7
8
6
9
6
9
5
9
4
9
3
9
2
9
1
9
0
8
9
104
119
120
121
124
125
126
2
9
3
1
109
3
3
46
107
123
127
2 1
116
117
R
O
M
_
A
D
D
R
5
P
V
D
D
2
P
V
S
S
2
ROM_ADDR9
ROM_ADDR13
ROM_ADDR8
ROM_ADDR7
ROM_ADDR6
ROM_ADDR12
ROM_ADDR16
ROM_ADDR17
ROM_ADDR14
GPIOA8/ROM_ADDR18
GPIOA9/ROM_ADDR19
PVDD1
HSYNC
GPIOA11
GPIOA10
PVSS1
VSYNC
DATA_TV7
DATA_TV6
DATA_TV5
G
P
IO
A
1
3
A
U
_
B
C
K
A
U
_
L
R
C
K
A
U
_
D
A
T
A
A
U
_
X
C
K
P
V
D
D
3
P
_
1
P
L
L
_
R
E
S
IS
T
O
R
P
V
S
S
3
P
_
1
P
V
D
D
3
P
_
0
P
V
S
S
3
P
_
0
G
P
IO
A
3
9
/P
A
L
_
N
T
S
C
G
P
IO
A
3
8
/C
L
K
2
7
_
O
U
T
P
V
D
D
2
P
V
S
S
2
G
P
IO
A
2
6
/C
L
K
IO
C
L
K
IN
DATA_TV0
DATA_TV1
DATA_TV2
DATA_TV3
DATA_TV4
D
A
8
D
A
7
D
A
6
D
A
5
D
A
4
D
A
0
D
A
1
D
A
2
D
A
3
R
O
M
_
D
A
T
A
3
R
O
M
_
D
A
T
A
4
R
O
M
_
D
A
T
A
2
R
O
M
_
D
A
T
A
5
R
O
M
_
D
A
T
A
1
R
O
M
_
D
A
T
A
6
R
O
M
_
D
A
T
A
0
R
O
M
_
D
A
T
A
7
R
O
M
_
A
D
D
R
1
R
O
M
_
A
D
D
R
3
R
O
M
_
A
D
D
R
4
R
O
M
_
A
D
D
R
1
1
P
V
S
S
1
P
V
D
D
1
W
E
_
B
C
A
S
_
B
R
A
S
0
_
B
D
D
1
1
D
D
1
0
D
D
9
D
D
8
VM
AIN
C
D
_
B
L
C
K
PVDD3P_2
P
V
S
S
2
GPIOA5/DA10
GPIOA4/DA9
GPIOA3/BA0
GPIOA2/DQM1
GPIOA1/DQM0
GPIOA0/RAS1_B/BA1
DD2
PVSS2
DD6
C
D
_
L
R
C
K
R
E
S
E
T
_
B
P
V
D
D
2
G
P
IO
B
4
0
/C
D
_
X
C
K
GPIOB41
G
P
IO
A
1
7
G
P
IO
A
1
6
G
P
IO
A
1
5
G
P
IO
A
1
4
G
P
IO
A
1
2
G
P
IO
A
2
0
G
P
IO
A
1
9
G
P
IO
A
1
8
C
D
_
D
A
T
A
P
V
D
D
1
P
V
S
S
1
G
P
IO
A
2
5
G
P
IO
A
2
4
G
P
IO
A
2
3
G
P
IO
A
2
2
G
P
IO
A
2
1
PVSS3P_2
DD3
DD4
DD5
DD15
DD14
DD13
R
O
M
_
A
D
D
R
0
R
O
M
_
A
D
D
R
2
GPIOA6
R
O
M
_
A
D
D
R
1
0
ROM_ADDR15
ATO
DD7
GPIOA7/SDRAM_CLK
D
D
1
2
P
V
D
D
2
DD0
DD1
R19
10K
BC4
0.1U
C15 82P
R29 OPEN
R123
10K
R13
33
R15
33
R27
2K
C16
1000P
R2
0
D1
1N4148
1
2
BC7
0.1U
BC5
0.1U