Wide, pipelined internal data path architecture
Optimized transmit (Tx) and receive (Rx) queues
32 KB configurable Rx and Tx first-in/first-out (FIFO)
IEEE 802.3x*-compliant flow-control support with software controllable pause
times and threshold values
Programmable host memory Rx buffers (256 B-16 KB)
Descriptor ring management hardware for Tx and Rx
Mechanism for reducing interrupts from Tx/Rx operations
Integrated PHY for 10/100/1000 Mbps (full- and half-duplex)
IEEE 802.3ab* auto-negotiation support
IEEE 802.3ab PHY compliance and compatibility
Tx/Rx IP, TCP, and UDP checksum offloading
Tx TCP segmentation
2.9 PCI Bus Components
The PCI interface edge connector is connected to the PCI bus on the backplane. The PCI
bus edge connector is shown below.
Figure 2-20: PCI Edge Connector
The PCI is interfaced to four standard PCI expansion cards on a compatible PICMG 1.3
backplane.
Page 36
Содержание 3308290
Страница 1: ...Page i User s Manual S PICMG 1 3 SBC 3308290 Versionx1 0 ...
Страница 10: ...Figure 5 21 USB Device Connection 103 Figure 5 22 VGA Connector 104 Page x ...
Страница 13: ...Chapter 1 1 Introduction Page 13 ...
Страница 19: ...Chapter 2 2 Detailed Specifications Page 19 ...
Страница 37: ...Page 37 ...
Страница 38: ...Page 38 ...
Страница 39: ...Page 39 ...
Страница 40: ...Chapter 3 3 Unpacking Page 40 ...
Страница 44: ...Chapter 4 4 Connector Pinouts Page 44 ...
Страница 77: ...5 Chapter 5 Installation Page 77 ...