Theory of Operation
Manual 21568, Rev. F, March 2008
U10C and U7A provide a fast Track and Hold (T&H). U7A buffers the T&H capacitor C21, and
U7B buffers the S&H capacitors, C1 & C2.
Figure 3-2: Analog PC Assembly Block Diagram
A track and hold differs from a sample and hold in the manner in which the signal prior to the
hold is manipulated. In a sample and hold, the sample gate turns on and the holding capacitor
is charged to the signal potential, then the sample gate turns off and the hold capacitor
maintains the value of the input at the time of the sample. In a track and hold circuit, the voltage
on the hold capacitor is the same as the input (tracks) until the track gate goes off, after which
the level is held until the track goes on and the hold capacitor again follows the input.
The INTernal or EXTernal trigger source is selected by U10D and U11A. U11B functions as an
inverter for HIGHGAIN. U6 amplifies the trigger signal by 1 or 41. Trigger DAC U9 is loaded
with a count from the serial chain. The DAC needs the data signal held after the clock for at
least 80 ns. A2R12 and A2C25 on the Digital board take care of that requirement. That count
gets translated into a voltage between -0.1 V and about +5 V by U8A. Digital board comparator
A2U18 provides the TRIG-IN pulse (A2TP25). A2R42 provides hysteresis for A2U18.
*
NOTE:
All times shown in Figure 3-3 are referenced to TP3, and are not to scale.
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