GE PCIE-5565PIORC*, Справочник по аппаратуре

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Programming 55
set high (1), the Global Interrupt Enable bit will automatically
be cleared as this register (LISR) is being read. This bit is read
and write accessible with this register and thus allows a
single read ‐ modify ‐ write operation to service the local
interrupts.
Bit 13: Local Memory Parity Error ‐ When this bit is high (1), one or
more parity errors have been detected on local memory
accesses. This bit is latched. Once set, it must be cleared by
writing a zero to this bit location. Note that Bit 27 of the
LCSR1 must be set high before parity is active. Also note that
parity works only on 32 ‐ bit and 64 ‐ bit accesses. Word (16 ‐ bit)
and byte (8 ‐ bit) memory write accesses are inhibited.
Bit 12: Memory Write Inhibited ‐ When this bit is high (1), an 8 ‐ bit
byte, a 16 ‐ bit word, or a 24 ‐ bit write to local memory was
attempted and inhibited while the board was in the parity
enabled mode. This bit is latched. Once set, it must be cleared
by writing a zero to this bit location.
Bit 11: Latched Sync Loss – When this bit is high (1), the receiver
circuit has lost synchronization with the incoming signal one
or more times. This bit is latched. Once set, it must be cleared
by writing a zero to this bit location. The assertion of the
Latched Sync Loss usually indicates the receiver link was or
is disconnected, either intentionally or unintentionally, and
data may have been lost. This event will also occur if the
upstream node tied to the receiver is powered off or is
disabled.
Bit 10: RX FIFO Full – When this bit is high (1), the RX FIFO has
been full one or more times. This bit is latched. Once set, it
must be cleared by writing a zero to this bit location. This is a
fault condition and data may have been lost.
NOTE
This condition should not occur during normal operation. Bit 10 is for diagnostic purposes only.
Bit 09 : RX FIFO Almost Full – When this bit is high (1), the RX FIFO
has been almost full one or more times. This bit is latched.
Once set, it must be cleared by writing a zero to this bit
location. The assertion of the RX FIFO Almost Full bit
indicates the receiver circuit is operating at maximum
capacity. If it does occur, the PCI bus master should
temporarily suspend all write and read operations to the
board.
Bit 08: Bad Data – When this bit is high (1), the receiver circuit has
detected invalid data one or more times. This bit is latched.
Once set, it must be cleared by writing a zero to this bit
location.