GE Mini COM Express 10, Справочник по аппаратуре

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6.8 Board Supervision Run-Time Registers
Board supervision run-time registers are listed in the following table. The address
indicates the offset from the base address programmed in the configuration register.
Supervision Run-Time Registers
Offset Name
Description
0x0 Reset Cause Cumulative reset cause indication
0x1 Last Reset Last reset cause indication
0x2
—
Unused
0x3 — Unused
6.8.1 Reset Cause
The Reset Cause register provides information to boot and recovery software regarding
the cause of the processor reset. A power-on reset will set the power-on event bit and
clear all the other event bits. Subsequent resets will set the corresponding event bits but
not affect any other bit. Reset cause indications are cleared by writing ones to the
associated register bit positions. Register bits written with zeroes are not affected.
Typically, this register should be read early in the boot process.
Note This register cannot detect software-controlled hard or soft resets issued by the
SoC.
Reset Cause Register (Offset 0x0)
Bit Name Access Default
Description
7
VREG_RST
R/C 0
When set, indicates that a CPU power
supply regulator under-voltage reset
occurred. Cleared by writing a 1 to the bit.
6
WDOG_RST
R/C 0
When set, indicates that a watchdog
timeout reset occurred. Cleared by writing
a 1 to the bit.
5 —
R 0 Unused
4
DB_RST
R/C 0
When set, indicates that a debug port
reset event occurred. Cleared by writing a
1 to the bit.
3
—
R 0 Unused
2
PB_RST
R/C 0
When set, indicates that a push-button
reset event occurred. Cleared by writing a
1 to the bit.
1 OVERTEMP R/C 0
When set, indicates that a processor
over-temperature alarm event occurred.
Cleared by writing a 1 to the bit.
0 POR R/C 1
When set, indicates that a power-on reset
event has occurred. Cleared by writing a 1
to the bit.
FPGA Registers GFK-2896 Hardware Reference Manual 65
For public disclosure