GS-EVB-HB-66508B-RN Technical Manual
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GS-EVB-HB-66508B-RN Rev. 210118 © 2021 GaN Systems Inc.
www.gansystems.com 3
Please refer to the Evaluation Board/Kit Important Notice on page 26
Table 2 Control pins
Pin
Descriptipon
ENABLE
Enable input. It is internally pulled up to VCC, a low logic disables all the PWM gate
drive outputs.
+5V
+5V auxillary power supply input for logic circuit and gate driver. On the daughter
board there are 2 isolated 5V to 9V DC/DC power supplies for top and bottom
switches.
VDRV
Not used. VDRV can be connected to VCC though R43. R43 is DNP by default.
PWMH_IN High side PWM logic input for top switch Q1. It is compatible wth 3.3V and 5V
PWML_IN Low side PWM logic input for bottom switch Q2. It is compatible wth 3.3V and 5V
0V
Logic inputs and gate drive power supply ground return.
The 3 power pins are:
•
VDC+: Input DC Bus voltage
•
VSW: Switching node output
•
VDC-: Input DC bus voltage ground return. Note that control ground 0V is isolated from VDC-
Figure 1 GS-EVB-HB-66508B-RN Evaluation Board Block Diagram
Isolator
IL611-1E
Q
1
Q
2
Iso
.
DC
/
DC
Iso
.
DC
/
DC
VDC
+
VSW
VDC
-
VCC
ENABLE
shunt
C
4
-
10
PWMH
PWML
Gate Driver
RAA226110
Gate Driver
Isolator
IL611-1E
RAA226110
