Gamry Instruments PCI4/300 Potentiostat/Galvanostat/ZRA, Руководство оператора

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Chapter 1 -- Introduction -- Potentiostat Schematic Diagram
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A few points concerning this schematic:
•
The circuits on the right side of the schematic are on the Potentiostat card and those on the left are on
the Controller Card. The dotted line shows the separation between the two portions of the
instrument. The analog signals sent between the portions are received in differential amplifiers to
eliminate grounding problems.
•
Arrows pointing into a circuit indicate a computer control input.
•
The labels CE , RE and WE stand for counter electrode, reference electrode and working electrode
respectively.
•
There are two 16 bit D/A converters generating the computer controlled portion of the applied cell
voltage.
•
The I/E converter uses a series resistor to measure the cell current. The circuit actually uses eight
decade resistors that can be switched in under computer control.
•
The cell switch is actually two switches in series - a relay for low leakage and an FET switch for fast
response.
• The label OLP refers to overload protection.
• Gains and resistor values are not shown.
•
Two capacitors can be switched across the I/E converter resistor. These capacitors are used for
filtering and stability compensation.
•
The control amplifier is shown at the upper right side of the schematic. Compensation capacitors can
be switched across the control amplifier to adjust its bandwidth and improve potentiostat stability.
•
The A/D converter is a 16 bit successive approximation type converter.
•
Some analog circuits, including overload detection circuitry, positive feedback IR compensation, the
auxiliary D/A converter, power circuits, and data acquisition controls are not shown.
• All digital circuits, including the AT bus interface, timers, state machines, opto-couplers, and digital I/O
are not shown.
•
Timing for both data acquisition and D/A update in the signal generator is controlled by a state
machine working with a crystal oscillator generated clock. A busy processor in the computer cannot
create timing jitter.