Fujitsu MPC3032AT, Руководство по эксплуатации продукта

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C141-E055-01EN 5 - 64
5.5.2 Phases of operation
An Ultra DMA data transfer is accomplished through a series of Ultra DMA data in or data out
bursts. Each Ultra DMA burst has three mandatory phases of operation: the initiation phase,
the data transfer phase, and the Ultra DMA burst termination phase. In addition, an Ultra
DMA burst may be paused during the data transfer phase (see 5.5.3 and 5.5.4 for the detailed
protocol descriptions for each of these phases, 5.6.4 defines the specific timing requirements).
In the following rules DMARDY- is used in cases that could apply to either DDMARDY- or
HDMARDY-, and STROBE is used in cases that could apply to either DSTROBE or
HSTROBE. The following are general Ultra DMA rules.
a) An Ultra DMA burst is defined as the period from an assertion of DMACK- by the host to
the subsequent negation of DMACK-.
b) A recipient shall be prepared to receive at least two data words whenever it enters or
resumes an Ultra DMA burst.
5.5.3 Ultra DMA data in commands
5.5.3.1 Initiating an Ultra DMA data in burst
The following steps shall occur in the order they are listed unless otherwise specifically
allowed (see 5.6.4.1 and 5.6.4.2 for specific timing requirements):
1) The host shall keep DMACK- in the negated state before an Ultra DMA burst is initiated.
2) The device shall assert DMARQ to initiate an Ultra DMA burst. After assertion of
DMARQ the device shall not negate DMARQ until after the first negation of DSTROBE.
3) Steps (3), (4) and (5) may occur in any order or at the same time. The host shall assert
STOP.
4) The host shall negate HDMARDY-.
5) The host shall negate CS0-, CS1-, DA2, DA1, and DA0. The host shall keep CS0-, CS1-,
DA2, DA1, and DA0 negated until after negating DMACK- at the end of the burst.
6) Steps (3), (4) and (5) shall have occurred at least t
ACK
before the host asserts DMACK-.
The host shall keep DMACK- asserted until the end of an Ultra DMA burst.
7) The host shall release DD (15:0) within t
AZ
after asserting DMACK-.
8) The device may assert DSTROBE t
ZIORDY
after the host has asserted DMACK-. Once the
device has driven DSTROBE the device shall not release DSTROBE until after the host
has negated DMACK- at the end of an Ultra DMA burst.
9) The host shall negate STOP and assert HDMARDY- within t
ENV
after asserting DMACK-.
After negating STOP and asserting HDMARDY-, the host shall not change the state of
either signal until after receiving the first transition of DSTROBE from the device (i.e.,
after the first data word has been received).
10) The device shall drive DD (15:0) no sooner than t
ZAD
after the host has asserted DMACK-,
negated STOP, and asserted HDMARDY-.