MB91F465XA EMULATION
Chapter 5 Appendix
© Fujitsu Microelectronics Europe GmbH
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MCU-AN-300015-E-V11
Bit
Name
Function
Bit 31
MBSUE:
Message buffer Status
update enable
This bit controls the Message buffer status update
ports: MBSU_RX1; MBSU_TX1, MBSU_TX2,
MBSU_RX2
"0": Disabled
"1": Enabled
<<Note>>
If enabled output “High” at every Message buffer
status update. High duration: One RAM clock cycle.
If “0“ is set outputs “L” at pin.
Bit 30
CYCSE:
Cycle start output
enable
This bit controls the Cycle start output
"0": Disabled
"1": Enabled
<<Note>>
If enabled output “High” at every cycle start. High
duration: One RAM clock cycle
If “0“ is set outputs “L” at pin.
Bit 29
MTE:
Start of Macrotick
output enable
This bit controls the Macrotick start output
"0"
:
Disabled
"1"
:
Enabled
<<Note>>
If enabled output “High” at every Macrotick start.
High duration: One RAM clock cycle
If “0“ is set outputs “L” at pin.
Bit 28
SDSE:
Start of dynamic
segment output enable
This bit controls the start of dynamic segment output
"0": Disabled
"1": Enabled
<<Note>>
If enabled Output “High” at every start of dynamic
segment. High duration: One RAM clock cycle
If “0“ is set outputs “L” at pin.
Bit 27
CYCS0E:
Start of cycle 0 output
enable
This bit controls the Cycle 0 start output
"0": Disabled
"1": Enabled
<<Note>>
If enabled output “High” at every cycle 0 start. High
duration: One RAM clock cycle
If “0“ is set outputs “L” at pin.
Bit 26 –
Bit 16
RSV: Reserved
These bits are reserved. "0" is read. Write "0".
Table 5-3: DBGS Bit description