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3. Details of hardware
MB86R11
Evaluation Board
MB86R11EVB Hardware Manual
SW1 (DISP0_DAC_CTRL)
Set SW1[2:1]=[OFF, OFF] when I2C0 is used.
SW1 Signal
Description
Default
(I2C mode)
1 DSEL
/
SDA
Dual edge clock select / I2C Data
This pin is an open collector input/output.
If I2C bus is enabled (ISEL=OFF), then this pin is the I2C data line.
If the I2C bus is disabled (ISEL=ON), then this pin selects whether single clock
dual edge is used.
Dual Edge clock select:
DSEL=OFF:
IDCK+ latches input data on both falling and rising clock edges.
DSEL=ON:
IDCK+/IDCK- latches input data on only falling or rising clock edges.
In 24-/12-bit mode:
DSEL=OFF (dual edge):
IDCK+ is used to latch data on both falling and rising edges.
DSEL=ON (single edge):
IDCK+ latches 1st half data and IDCK- latches 2nd half data.
OFF
2 BSEL
/
SCL
Input bus select / I2C clock.
This pin is an open collector input.
If I2C bus is enabled (ISEL=OFF), then this pin is the I2C clock input.
If the I2C is disabled (ISEL=ON), then this pin selects the input bus width.
Input Bus Select:
BSEL=OFF:
selects 24-bit input mode
BSEL=ON:
selects 12-bit input mode
OFF
3 EDGE
/
HTPLG
Edge select / Hot Plug input.
If the I2C bus is enabled (ISEL=OFF), then this pin is used to monitor the "Hot
Plug" detect signal (Please refer to the DVI or VESA P&D and DFP standards).
This Input is ONLY 3.3V tolerant and has no internal de-bouncer circuit.
If I2C bus is disabled (ISEL=ON), then this pin selects the clock edge that will
latch the data. How the EDGE setting works depends on whether dual or single
edge latching is selected.
Dual Edge Mode (DSEL = OFF)
EDGE=ON:
the primary edge (first latch edge after DE is asserted) is the falling edge.
EDGE=OFF:
the primary edge (first latch edge after DE is asserted) is the rising edge.
(Note)
In 24-bit Single Clock Dual Edge mode, EDGE is ignored.
Single Edge Mode (DSEL=ON)
EDGE=ON:
the falling edge of the clock is used to latch data.
EDGE=OFF:
the rising edge of the clock is used to latch data.
OFF
ON
8 1
Default
