Mainboard Users Manual
40
4.4.1.
DRAM Clock/Drive Control
Scroll to this item and press <Enter> to view the following screen:
DRAM Clock:
This item allows you to control the DRAM speed. The
default setting is Host CKL.
DRAM Timing:
Set this By SPD to Enabled the system to automatically
set the SDRAM timing by SPD (Serial Presence Detect). SPD is an
EEPROM chip on the DIMM module that stores information about the
memory chips it contains, including size,speed, voltage row and column
addressed, and manufcturer. If you disable this item, you can use the
following two items to manually set the timing parameters for the system
memory. The default setting is Enabled.
Advanced Chipset Features
Содержание P6F212
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