Hardware Description
TWR-P1025 Hardware User Guide, Rev. 0
4
Freescale Semiconductor
Two DIP switches (SW1[7:8]) select the core/QE frequencies. Three modes run at 66.667MHz SYSCLK
whereas the 4th mode is for Profibus application and uses the 64 MHz SYSCLK.
The DDR runs at a fixed x10 multiplier to DDR_CLK.
Table 3-1. P1025 CCB to SYSCLK Ratio Selection
Functional Signals
Reset Configuration Name
Value
CCB Clock : SYSCLK Ratio
LA[29:31] No Default
cfg_sys_pll[0:2]
000
4:1
001
5:1
010
6:1
Table 3-2. P1025 e500 Core 0 & 1 to CCB Clock Ratio Selection
Functional Signals
Reset Configuration
Name
Value
e500 Core: CCB Clock
Ratio
LBCTL, LALE,
LGPL2/LOE/LFRE
No Default
LWE0, UART_SOUT1,
READY_P1
No Default
cfg_core0_pll[0:2]
cfg_core1_pll[0:2]
000
Reserved
001
Reserved
010
1:1
011
3:2 (1.5:1)
100
2:1
101
5:2 (2.5:1)
110
3:1
111
Reserved
Table 3-3. P1025 DDR Clock PLL Ratio
Functional Signals
Reset Configuration
Name
Value
e500 Core: CCB Clock
Ratio
TSEC_1588_CLK_OUT,
TSEC_1588_PULSE_OUT1,
TSEC_1588_PULSE_OUT2
No Default
cfg_ddr_pll[0:2] 000
3:1
001
4:1
010
6:1
011
8:1
100
10:1
101
Reserved
110
Reserved
111
Synchronous mode