Figure 7. Port map
6.4 Known issues
The T4240RDB has the following known issues:
• XFI: Two 10 Gbps (ETH10, ETH11) are not working; other two 10 Gbps (ETH8 , ETH9) are working fine.
NOTE
This is a limitation of T4240 Rev 1.0 silicon, and will be resolved with Rev 2.0 silicon.
7 Default boot mode
In the T4240RDB, the boot loader, by default, executes from the NOR flash.
8 Switch settings
8.1 SW1 switch
The SW1 switch is used to control system clock (SYSCLK) and DDR reference clock (DDRCLK). The table below shows
the SW1 settings for SYSCLK/DDRCLK ratio 4:1.
Table 2. SW1 Settings
4:1
CPU Speed
SYSCLK(MHz)
DDRCLK(MHz)
0000
1667
66.67
66.67
0001
1667
66.67
100
0010
1667
66.67
125
0011(Default)
1667
66.67
133.33
0100
1600
100
66.67
0101
1600
100
100
0110
1600
100
125
0111
1600
100
133.33
1000
X
125
66.67
Table continues on the next page...
Default boot mode
T4240RDB Quick Start Guide, Rev 0, 11/2013
Freescale Semiconductor, Inc.
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