Freescale Semiconductor QorIQ LS1043A, Справочное руководство

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CPLD memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
E Global reset register (CPLD_GLOBAL_RST) 8 R/W 00h 6.1.15/60
F
TDM riser card presence detection register
(CPLD_TDMR_PRS_N)
8 R 01h 6.1.16/61
10 RTC clock assignment register (CPLD_REG_RTC) 8 R/W 00h 6.1.17/61
6.1.1 CPLD major version register (CPLD_VER)
Use this register to specify CPLD major version.
Address: 0h base + 0h offset = 0h
Bit 0 1 2 3 4 5 6 7
Read VER
Reserved
Write
Reset 0 0 0 0 0 0 0 1
CPLD_VER field descriptions
Field Description
0–3
VER
CPLD major version
4–7
-
This field is reserved.
6.1.2 CPLD minor version register (CPLD_VER_SUB)
Use this register to specify CPLD minor version.
Address: 0h base + 1h offset = 1h
Bit 0 1 2 3 4 5 6 7
Read VER_SUB
Reserved
Write
Reset
0 0 0 0 0 0 1 1
CPLD memory map / register definitions
QorIQ LS1043A Reference Design Board Reference Manual, Rev. 0, 08/2015
52 Freescale Semiconductor, Inc.