Freescale Semiconductor QorIQ LS1043A, Справочное руководство

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3.2.2 Power sequencing
After 12 V power supply becomes available on the board, all power rails feeding the
LS1043ARDB are automatically turned ON and sequenced by CPLD. Power is enabled
in the following sequence:
1. TVDD, AVDD_SD1_PLL1, AVDD_SD1_PLL2, OVDD, DVDD, LVDD, EVDD,
USB_HVDD, X1VDD
2. Core VDD, S1VDD, TA_BB_VDD, USB_SDVDD, USB_SVDD
3. G1VDD, DDR_VREF, DDR_VTT
3.3 CPLD controller
The LS1043ARDB complex programmable logic device (CPLD) controller allows you to
control the functionality of the board. CPLD is powered from the local power supplies
and gets clock input from an independent oscillator. This allows CPLD to control all
aspects of board bring-up, including memory and reset. CPLD is implemented in a
Lattice LCMXO1200C-3FTN256C, 256-ball BGA.
3.3.1 CPLD features
The LS1043ARDB contains a CPLD controller that implements the following functions:
• Reset signal generation and distribution. System reset features are:
• Power-on reset (POR) for the LS1043A processor, NOR flash, PCIe, DDR, and
PHY devices with initialization of all CPLD registers to their default values.
• Manual reset: System resets and initializes all CPLD registers to their default
values, after pressing the reset button.
• Global register reset: Set register to reset the whole system, initializing all CPLD
registers to their default values.
• Local register reset: Set register to reset the whole system, maintaining all CPLD
registers' current values.
• Power sequencing for the LS1043A regulators, including core VDD, GVDD, and
others powers.
• Control POR sequencing: Configure the POR signals according to the external DIP
switches or board requests.
• Control status LED
• Map/re-map the LS1043A local bus chip selects and ready and busy signals to NOR
flash and NAND flash
• IFC bus control:
Chapter 3 Power Supplies and CPLD Controller
QorIQ LS1043A Reference Design Board Reference Manual, Rev. 0, 08/2015
Freescale Semiconductor, Inc. 35