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MOTOROLA

Chapter 7. Electrical Characteristics

7-3

PRELIMINARYÑSUBJECT TO CHANGE WITHOUT NOTICE

Figure 7-2. MII Transmit Signal Timing Diagram

7.3.3 MII Async Inputs Signal Timing (CRS, COL)

Table 7-3 provides information on the MII async inputs signal timing, shown in Figure 7-3.

Figure 7-3 shows the MII asynchronous inputs signal timing diagram.

Figure 7-3. MII Async Inputs Timing Diagram

Table 7-3. MII Async Inputs Signal Timing

Num

Characteristic

Min

Max

Unit

CRS, COL minimum pulse width

1.5

TX_CLK period

TX_CLK (input)

TXD[3:0] (outputs)
TX_EN
TX_ER

CRS, COL

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Содержание MPC860T

Страница 1: ...TICE MPC860TAD D Rev 0 8 09 1999 MPC860T Rev D Fast Ethernet Controller Supplement to the MPC860 PowerQUICC User s Manual Freescale Semiconductor I Freescale Semiconductor Inc For More Information On...

Страница 2: ...e body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may o...

Страница 3: ...criptions 2 1 Chapter 3 Fast Ethernet Controller Operation 3 1 Transceiver Connection 3 1 3 2 FEC Frame Transmission 3 2 3 3 FEC Frame Reception 3 3 3 4 CAM Interface 3 4 3 5 FEC Command Set 3 4 3 6 E...

Страница 4: ...ES_START 6 5 6 2 7 Receive Buffer Size Register R_BUFF_SIZE 6 6 6 2 8 Ethernet Control Register ECNTRL 6 7 6 2 9 Interrupt Event I_EVENT Interrupt Mask Register I_MASK 6 8 6 2 10 Ethernet Interrupt Ve...

Страница 5: ...r RxBD 6 24 6 4 2 Ethernet Transmit Buffer Descriptor TxBD 6 26 Chapter 7 Electrical Characteristics 7 1 DC Electrical Characteristics 7 1 7 2 AC Electrical Characteristics 7 1 7 3 Electrical Specific...

Страница 6: ...troller Supplement MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE CONTENTS Paragraph Number Title Page Number Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This...

Страница 7: ...sters 6 8 6 10 IVEC Register 6 10 6 11 R_DES_ACTIVE Register 6 11 6 12 X_DES_ACTIVE Register 6 12 6 13 MII_DATA Register 6 13 6 14 MII_SPEED Register 6 14 6 15 R_BOUND Register 6 15 6 16 R_FSTART Regi...

Страница 8: ...troller Supplement MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE ILLUSTRATIONS Figure Number Title Page Number Freescale Semiconductor I Freescale Semiconductor Inc For More Information On Thi...

Страница 9: ...0 I_EVENT I_MASK Field Descriptions 6 9 6 11 IVEC Field Descriptions 6 10 6 12 R_DES_ACTIVE Field Descriptions 6 11 6 13 X_DES_ACTIVE Field Descriptions 6 12 6 14 MII_DATA Field Descriptions 6 13 6 15...

Страница 10: ...criptor RxBD Field Description 6 25 6 29 Transmit Buffer Descriptor TxBD Field Descriptions 6 26 7 1 MII Receive Signal Timing 7 2 7 2 MII Transmit Signal Timing 7 2 7 3 MII Async Inputs Signal Timing...

Страница 11: ...to the MPC8xx family with its incorporation of a Fast Ethernet communication controller The 10 100 Fast Ethernet controller with integrated FIFOs and bursting DMA is implemented independently so high...

Страница 12: ...ssing and 10 100 Ethernet in one chip makes the MPC860T ideal for products such as high performance low cost remote access routers Note that for existing parts adding FEC functionality affects port D...

Страница 13: ...tomatic interrupt vector generation for receive and transmit events Tx interrupts Rx interrupts and non time critical interrupts Ethernet channel uses DMA burst transactions to transfer data to and fr...

Страница 14: ...emory allowing the FIFO to be ushed in the event of a runt or collided frame with no DMA activity However external memory for buffers and BDs is required on chip FIFOs are designed only to compensate...

Страница 15: ...CLK is shared with IRQ7 and becomes active as soon as the ETHER_EN bit in the Ethernet control register ECNTRL is set IRQ7 must be masked in the system interface unit SIU 1 5 Glueless System Design A...

Страница 16: ...l channels to physical layer framers and transceivers Figure 1 3 MPC860T Serial Configuration 7 wire interface MPC8xx 100Base T Transceiver 10Base T Transceiver T1 Framer TDM SCC2 QMC SCC3 QMC RS 232...

Страница 17: ...active as soon as the ETHER_EN bit in the Ethernet control register ECNTRL is set IRQ7 must be masked in the system interface unit SIU PD 15 L1TSYNCA MII_RXD 3 U17 General purpose I O port D bit 15 T...

Страница 18: ...XD 1 3 are ignored PD 8 TXD4 MII_RX_CLK W17 General purpose I O port D bit 8 This is bit 8 of the general purpose I O port D TXD4 Transmit data for serial channel 4 MII receive clock Input clock which...

Страница 19: ...wing the nal nibble of the frame Note the following For 860T rev D 1 a 10 kW pull down resistor must be used with MII_TX_EN which is three stated following reset until ECNTRL FEC_PINMUX is set For 860...

Страница 20: ...ev D Fast Ethernet Controller Supplement MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www free...

Страница 21: ...eive Control Register R_CNTRL Table 3 1 shows the 18 MII interface signals that are de ned by the 802 3 standard Serial mode connections to the external transceiver are shown in Table 3 2 Table 3 1 MI...

Страница 22: ...reached The FEC stores the rst 64 bytes of the transmit frame in internal RAM so that they do not have to be retrieved from system memory in case of a collision This improves bus usage and latency in...

Страница 23: ...D0 after RX_DV RENA is asserted are ignored Following the rst 16 bit times the data sequence is checked for alternating ones and zeros If a 11 or 00 sequence is detected during bit times 17 to 21 the...

Страница 24: ...4 CAM Interface In addition to the FEC address recognition logic an external CAM may be used for frame reject with no additional pins other than the MII interface pins For more information on the CAM...

Страница 25: ...ived without the MISS bit being set Figure 3 1 Ethernet Address Recognition Flowchart 3 7 Hash Table Algorithm This section discusses the hash table process used in group hash ltering When the FEC rec...

Страница 26: ...sh is as follows 3 8 Inter Packet Gap Time The minimum inter packet gap time for back to back transmission is 96 bit times After completing a transmission or after the backoff algorithm completes the...

Страница 27: ...rame the FEC sets the CSL bit in the last TxBD for this frame The frame is sent normally No retries are performed as a result of this error The CSL bit is not set if X_CNTRL FDEN 1 regardless of the s...

Страница 28: ...y If there is a CRC error the frame nonoctet aligned NO error is reported in the RxBD If there is no CRC error no error is reported CRC Error When a CRC error occurs with no dribbling bits the FEC clo...

Страница 29: ...is con gured as an input if the corresponding PDDIR bit is cleared it is con gured as an output if the corresponding PDDIR bit is set All PDPAR bits and PDDIR pins are cleared on total system reset co...

Страница 30: ...s PDDIR 0 PDDIR 1 PD15 PORT D15 L1TSYNCA MII RXD3 I L1TSYNCA GND PD14 PORT D14 L1RSYNCA MII RXD2 I L1RSYNCA GND PD13 PORT D13 L1TSYNCB MII RXD1 I L1TSYNCB GND PD12 PORT D12 L1RSYNCB MII MDC O L1RSYNCB...

Страница 31: ...PM wins the rst access If both continue to request the SDMA hardware control alternates between the two Figure 5 1 SDMA Bus Arbitration The priority of the SDMA on the 60x bus is programmed in SDCR RA...

Страница 32: ...hese bits are reserved and should be cleared 17 FRZ Freeze Determines the action to be taken when the FRZ signal is asserted The SDMA negates BR and keeps it that way until the FRZ signal is negated o...

Страница 33: ...ract global status information The BDs are used to pass data buffers and related buffer information between hardware and software Some registers are located in on chip RAM All on chip registers whethe...

Страница 34: ...II data register 6 2 13 0xE84 MII_SPEED MII speed register 6 2 14 0xECC R_BOUND End of FIFO RAM read only 6 2 15 0xED0 R_FSTART Receive FIFO start address 6 2 16 0xEE4 X_WMRK Transmit Watermark 6 2 17...

Страница 35: ...dress recognition for receive frames with a multicast address It is written by and must be initialized by the user Table 6 2 ADDR_LOW Field Descriptions Bits Name Description 0 31 ADDR_LOW Bytes in th...

Страница 36: ...5 26 27 28 29 30 31 Field HASH_HIGH Reset Unde ned R W Read write Addr 0xE0A Figure 6 3 HASH_TABLE_HIGH Register Table 6 4 HASH_TABLE_HIGH Field Descriptions Bits Name Description 0 31 HASH_HIGH Conta...

Страница 37: ...s pointer should be quad word aligned Bits 30 and 31 should be cleared by the user hardware ignores non zero values in these bits It is written by the user is not reset and must be initialized by the...

Страница 38: ...BUFF_SIZE must be at least 0x0000_05F0 To ensure that R_BUFF_SIZE is a multiple of 16 bits 28 31 are forced to zeros Using buffers smaller than the recommended minimum 256 bytes increases the risk of...

Страница 39: ...e ned R W Read write Addr 0xE1A Figure 6 7 R_BUFF_SIZE Register Table 6 8 R_BUFF_SIZE Field Descriptions Bits Name Description 0 20 Reserved Should be written to zero by the host processor 21 27 R_BUF...

Страница 40: ...zero 29 FEC_PINMUX FEC enable Read write The user must set this bit to enable the FEC function in the 860 in conjunction with 860 pin multiplexing control 30 ETHER_EN Ethernet enable 0 A transfer is...

Страница 41: ...ndicates that the transmitted frame exceeded MAX_FRAME_LENGTH bytes This condition is usually caused by too large a a frame being placed into the transmit data buffers The transmit frame is not trunca...

Страница 42: ...13 14 15 Field ILEVEL Reset 0000_0000_0000_0000 R W Read write Addr 0xE4C Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Field IVEC Reset 0000_0000_0000_0000 R W Read only Addr 0xE4E Figure 6 10...

Страница 43: ...nd polling stops until the bit is set signifying additional BDs have been placed into the TxBD ring X_DES_ACTIVE is cleared at reset and by clearing ECNTRL ETHER_EN Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 1...

Страница 44: ...lows MII_DATA and MII_SPEED to be programmed in either order if MII_SPEED is currently zero MII_DATA is accessed by the user and does not reset to a de ned value Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 1...

Страница 45: ...control logic to shift data out of MII_DATA following a preamble generated by the control state machine During this time the contents of MII_DATA are serially shifted and are unpredictable if read by...

Страница 46: ...I_SPEED must Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field Reset 0000_0000_0000_0000 R W Read write Addr 0xE84 Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Field DIS_PREAMBLE MII_SPEED Rese...

Страница 47: ...e the upper address bound of the FIFO RAM Drivers can use this value along with the R_FSTART and X_FSTART to appropriately divide the available FIFO RAM between the transmit and receive data paths Tab...

Страница 48: ...smission of a frame can begin This allows the user to minimize transmit latency X_WMRK 0x or allow larger bus access latency X_WMRK 11 due to contention 22 29 R_BOUND Read only Highest valid FIFO RAM...

Страница 49: ...ue Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field Reset 0000_0000_0000_0000 R W Read write Addr 0xED0 Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Field X_WMRK Reset 0000_0000_0000_0000 R W...

Страница 50: ...d 1 X_FSTART Reset 0000_0 1 Microcode dependent 00 R W Read write Addr 0xEEE Figure 6 18 X_FSTART Register Table 6 20 X_FSTART Field Descriptions Bits Name Description 0 21 Reserved Note that all bits...

Страница 51: ...The byte order eld supplied to the SDMA interface during receive and transmit open descriptor DMA transfers and during close descriptor DMA transfers 00 Reserved 01 PowerPC little endian byte ordering...

Страница 52: ...ardless of address matching 29 MII_MODE Selects external interface mode for both transmit and receive blocks 0 Selects seven wire mode used only for serial 10 Mbps 1 Selects MII mode 30 DRT Disable re...

Страница 53: ...D The recommended value to be programmed by the user is 1518 or 1522 if VLAN tags are supported Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field Reset 0000_0000_0000_0000 R W Read write Addr 0xF84 Bit...

Страница 54: ...t stop When GTS is set the MAC stops transmission after any frame being transmitted is complete and INTR_EVENT GRA is set If frame transmission is not underway the GRA interrupt is asserted immediatel...

Страница 55: ...6 3 2 2 User Initialization after Asserting ECNTRL ETHER_EN The user must initialize portions of the FEC after setting ECNTRL ETHER_EN The exact values depend on the application The sequence resembles...

Страница 56: ...et to point to the starting TxBDs and RxBDs The BDs are not initialized by hardware during reset At least one TxBD and one RxBD must be initialized by software write 0x0000_0000 to the most signi cant...

Страница 57: ...t were agged as a miss by the internal address recognition Thus while promiscuous mode is being used the user can use the M bit to quickly determine whether the frame was destined to this station This...

Страница 58: ...s buffer if L 0 the value R_BUFF_SIZE or the length of the frame including CRC if L 1 It is written by the FEC once as the BD is closed Offset 4 Rx buffer pointer Rx buffer pointer A 0 31 written by u...

Страница 59: ...f L 1 Set to indicate that a collision occurred after 56 data bytes were transmitted The FEC terminates the transmission 9 RL Retransmission limit written by FEC valid if L 1 Set to indicate that the...

Страница 60: ...Rev D Fast Ethernet Controller Supplement MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www fre...

Страница 61: ...characterization and device quali cations are completed 7 1 DC Electrical Characteristics MPC860T DC electrical characteristics are identical to those of the MPC860 The MII output signals that are ne...

Страница 62: ...irement In addition the processor clock frequency must exceed the TX_CLK frequency 1 Figure 7 2 shows the MII transmit signal timing diagram Table 7 1 MII Receive Signal Timing Num Characteristic Min...

Страница 63: ...al timing shown in Figure 7 3 Figure 7 3 shows the MII asynchronous inputs signal timing diagram Figure 7 3 MII Async Inputs Timing Diagram Table 7 3 MII Async Inputs Signal Timing Num Characteristic...

Страница 64: ...iming diagram Figure 7 4 MII Serial Management Channel Timing Diagram Table 7 4 MII Serial Management Channel Timing Num Characteristic Min ns Max ns Unit M10 MDC falling edge to MDIO output invalid m...

Страница 65: ...18 BSA0 GPLA0 NC CS6 GPLA5 BDIP CS2 PA14 A8 TEA PB28 PC13 PB29 VDDH VDDH BI BG CS3 PA13 BB PB27 PC12 VDDH GND GND TS IRQ3 VDDH PA12 BURST PB26 TMS PA11 IRQ6 IPB4 BR TDO IPB3 TRESET M_MDIO TCK IRQ2 IPB...

Страница 66: ...ev D Fast Ethernet Controller Supplement MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www free...

Страница 67: ...LA Chapter 7 ElectricalCharacteristics 7 7 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale c...

Страница 68: ...Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc...

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