MOTOROLA
Chapter 5. SDMA Bus Arbitration and Transfers
5-1
PRELIMINARYÑSUBJECT TO CHANGE WITHOUT NOTICE
Chapter 5
SDMA Bus Arbitration and Transfers
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This chapter describes SDMA functions speciÞc to the MPC860T, particularly where the
functionality differs from the MPC860. For a full discussion of SDMA bus arbitration and
transfers, refer to the
MPC860 PowerQUICC UserÕs Manual
.
5.1 Overview
The MPC860T has two arbitration levels to considerÑaccesses to the SDMA hardware and
accesses to the 60x bus. As shown in Figure 5-1, if the CPM and the 100BASE-T module
attempt to access the SDMA simultaneously, the CPM wins the Þrst access. If both continue
to request the SDMA hardware, control alternates between the two.
Figure 5-1. SDMA Bus Arbitration
The priority of the SDMA on the 60x bus is programmed in SDCR[RAID], described in
Section 5.2.1, ÒSDMA ConÞguration Register (SDCR).Ó
5.2 The SDMA Registers
This supplement describes the portions of the SDMA that differ from the MPC860. For a
thorough description of the SDMA, refer to the
MPC860 PowerQUICC UserÕs Manual
.
The SDMA channels share a conÞguration register, address register, and status register, and
are controlled by the conÞguration of the SCCs, SMCs, SPI, and I
2
C controllers.
CLK
TS
TA
Other cycle
SDMA cycle
Other cycle
SDMA internally
requests the bus
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