MPC8349EA MDS Processor Board HW Getting Started Guide, Rev. A
Freescale Semiconductor
Page 5 of 8
Step 3.d: SW7 Configuration
Set 4
SW7.1-SW7.7: Core PLL setting
Sets the ratio between the e300 core clock and the internal csb_clk
Factory setting: ‘000010000’ for core_clk = 533MHz
Recommended secondary setting: ‘00000110’ for core_clk = 500MHz
SW7.8: Core disable
Factory setting: '0'; core enabled for boot operation
Factory default setting: 00001000
Step 3.e: SW2 Software Option
SW2: Software option
Software BCS rotary-switch SW2 positions (0-7) enable program flow change
Switch status can be seen in BCSR10[2-4]
Factory setting: ‘0’
ON
PCB
Step 3.f: SW5 Power Switch
SW5: power switch
ON: power from an external 5V power supply via the P10 power jack
combined mode: powered from +5V on PIB power supply through riser
connectors (regardless of SW5 position)
board plugged as a PCI add-in card: PC internal power supply will provide 5V
via PCI edge connector (regardless of SW5 position)
Step 3.g: JP1:
Internal/External Clock
JP1
Selects the source for the CLOCKIN signal
• If a jumper is located between JP1 pins 1-2 (factory setting), the processor is
clocked from the on-board clock oscillator (U21 socket)
• If a jumper is located between JP1 pins 2-3, the processor is clocked from an
external source (via P5)
• The SHMOO mode clock source is I2C; manually programmed clock
synthesizer residing on PIB
2
1
3
2
1
3
Internal
Clock Source
External
Clock Source
1 <-
->0
1:
COREPLL0
ON
2:
COREPLL1
3:
COREPLL2
4:
COREPLL3
5:
COREPLL4
6:
COREPLL5
7:
COREPLL6
8:
COREDIS
12
3
4
5
6
7
8
5
0
