Freescale Semiconductor MPC5565, Справочное руководство

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Deserial Serial Peripheral Interface (DSPI)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 19-53
19.4.6.2 PCS to SCK Delay (t
CSC
)
The PCS x to SCK x delay is the length of time from assertion of the PCS x signal to the first SCK x edge.
Refer to Figure 19-32 for an illustration of the PCS x to SCK x delay. The PCSSCK and CSSCK fields in
the DSPI x _CTAR n registers select the PCS x to SCK x delay, and the relationship is expressed by the
following formula:
Table 19-23 shows an example of the computed PCS to SCK delay.
19.4.6.3 After SCK Delay (t
ASC
)
The after SCK x delay is the length of time between the last edge of SCK x and the negation of PCS x . Refer
to Figure 19-32 and Figure 19-33 for illustrations of the after SCK x delay. The PASC and ASC fields in
the DSPI x _CTAR n registers select the after SCK delay. The relationship between these variables is given
in the following formula:
Table 19-24 shows an example of the computed after SCK delay.
19.4.6.4 Delay after Transfer (t
DT
)
The delay after transfer is the length of time between negation of the PCS x signal for a frame and the
assertion of the PCS x signal for the next frame. The PDT and DT fields in the DSPI x _CTAR n registers
select the delay after transfer.
Refer to Figure 19-32 for an illustration of the delay after transfer.
The following formula expresses the PDT/DT/delay after transfer relationship:
Table 19-23. PCS to SCK Delay Computation Example
PCSSCK
Prescaler
Value
CSSCK
Scaler
Value
f
SYS
PCS to SCK Delay
0b01 3 0b0100 32 100 MHz 0.96
μ
s
Table 19-24. After SCK Delay Computation Example
PASC
Prescaler
Value
ASC
Scaler
Value
f
SYS
After SCK Delay
0b01 3 0b0100 32 100 MHz 0.96
μ
s
t
CSC
=
f
SYS
CSSCK
×
PCSSCK
1
×
t
ASC
=
f
SYS
ASC
×
PASC
1
×
t
DT
=
f
SYS
DT
×
PDT
1
×