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Pulse-Width Modulation (PWM) Module
MCF52110 ColdFire® Integrated Microcontroller Reference Manual, Rev. 1
26-12
Freescale Semiconductor
Preliminary
26.2.12 PWM Shutdown Register (PWMSDN)
The PWM shutdown register provides emergency shutdown functionality of the PWM module. The
PWMSDN[7:1] bits are ignored if PWMSDN[SDNEN] is cleared.
Table 26-12. PWMDTY
n
Field Descriptions
Field
Description
7–0
DUTY
Contains the duty value used to determine when a transition occurs on the PWM output signal. When a match occurs
with the corresponding PWMCNT
n
register, the PWM output toggles.
If DUTY equals 0x00, the PWM
n
output is always low (PPOL
n
=1) or always high (PPOL
n
for other special cases.
IPSBAR
Offset:
0x1B_0024 (PWMSDN)
Access: Read/Write
7
6
5
4
3
2
1
0
R
IF
IE
0
LVL
0
PWM7IN
PWM7IL
SDNEN
W
w1c
RESTART
Reset:
0
0
0
0
0
0
0
0
Figure 26-13. PWM Shutdown Register (PWMSDN)
Table 26-13. PWMSDN Field Descriptions
Field
Description
7
IF
PWM interrupt flag. Any change in state of PWM7IN is flagged by setting this bit. The flag is cleared by writing a ‘1’
to it. Writing ‘0’ has no effect.
0 No change in PWM7IN input
1 Change in PWM7IN input
6
IE
PWM interrupt enable. An interrupt is triggered to the device’s interrupt controller when PWMSDN[IF] is set.
0 Interrupt is disabled
1 Interrupt is enabled
5
RESTART
PWM restart. After setting the RESTART bit, the PWM channels start running after the corresponding counter resets
to zero. Also, if emergency shutdown is cleared (after being set), the PWM outputs restart after the corresponding
counter resets to zero. This bit is self-clearing, so is always read as zero.
4
LVL
PWM shutdown output level. Describes the behavior of the PWM outputs when PWM7IN input is asserted and
PWMSDN[SDNEN] is set.
0 PWM outputs are forced to logic 0
1 PWM outputs are forced to logic 1
3
Reserved, should be cleared.
2
PWM7IN
PWM channel 7 input status. Reflects the current status of the PWMOUT7 pin. Read only.