Freescale Semiconductor MC9S12ZVHL32, Справочное руководство

Страница: 172 / 874

Chapter 5 Background Debug Controller (S12ZBDCV2)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
172 Freescale Semiconductor
drive at the latest after 6 clock cycles, before the target drives a brief high speedup pulse seven target clock
cycles after the perceived start of the bit time. The host should sample the bit level about 10 target clock
cycles after it started the bit time.
Figure 5-7. BDC Target-to-Host Serial Bit Timing (Logic 1)
Figure 5-8 shows the host receiving a logic 0 from the target. The host initiates the bit time but the target
finishes it. Since the target wants the host to receive a logic 0, it drives the BKGD pin low for 13 target
clock cycles then briefly drives it high to speed up the rising edge. The host samples the bit level about 10
target clock cycles after starting the bit time.
HOST SAMPLES BKGD PIN
10 CYCLES
BDCSI clock
(TARGET MCU)
HOST DRIVE
TO BKGD PIN
TARGET MCU
SPEEDUP PULSE
PERCEIVED START
OF BIT TIME
HIGH-IMPEDANCE
HIGH-IMPEDANCE HIGH-IMPEDANCE
BKGD PIN
R-C RISE
10 CYCLES
EARLIEST START
OF NEXT BIT