
Data Transfer Modes
MC13192/MC13193 Technical Data, Rev. 2.7
Freescale Semiconductor
7
Figure 4. System Level Block Diagram
Figure 5. MC13192/MC13193 Packet Structure
Analog Receiver
MC13192/MC13193
Frequency
Generation
Analog
Transmitter
Voltage
Regulators
Power Up
Management
Control
Logic
Buffer RAM
Dig
ita
l T
ran
sc
ei
ve
r
SPI
and GPIO
Microcontroller
SPI
ROM
(Flash)
RAM
CPU
A/D
Ti
m
er
Application
IR
Q Ar
bi
te
r
RA
M Ar
bi
te
r
Tim
er
Network
MAC
PHY Driver
Preamble
SFD
FLI
Payload Data
FCS
4 bytes
1 byte
1 byte
125 bytes maximum
2 bytes