User’s Manual
M68HC12A4EVB Evaluation Board — Rev. 1
136
D-Bug12 Customization Data
MOTOROLA
D-Bug12 Customization Data
D.2.1 C Format
typedef struct {
Byte UserCCR;
/* User CPU Condition Code Register */
Byte UserB;
/* User CPU B-accumulator */
Byte UserA;
/* User CPU A-accumulator */
Address UserX;
/* User CPU X-index register */
Address UserY;
/* User CPU Y-index register */
Address UserPC;
/* User CPU Program Counter */
Address UserSP;
/* User CPU Stack Pointer */
unsigned long SysClk;
/* System Clock frequency (in Hz) */
Address IOBase;
/* Base address of the I/O registers */
unsigned int SCIBaudRegVal;
/* Initial SCI BAUD register value */
Address EEBase;
/* Base address of on-chip EEPROM */
unsigned int EESize;
/* size of the on-chip EEPROM */
void (*Delay)(void);
/* pointer to EEPROM program/erase */
/* delay routine */
int AuxCmdCount;
/* number of commands in the */
/* auxiliary command table */
CmdTblEntryP AuxCmdTableP;
/* pointer to the auxiliary command */
/* table */
} CustomData;
D.2.2 Assembly Format
org
$FE80
;
CustData
equ
*
UserCCR
dc.b
$90
; User CPU Condition Code Register
UserB
dc.b
$00
; User CPU B-accumulator
UserA
dc.b
$00
; User CPU A-accumulator
UserX
dc.w
$0000
; User CPU X-index register
UserY
dc.w
$0000
; User CPU Y-index register
UserPC
dc.w
$0000
; User CPU Program Counter
UserSP
dc.w
$0A00
; User CPU Stack Pointer
SysClk
dc.l
8000000
; System Clock frequency (in Hz)
IOBase
dc.w
$0000
; Base address of the I/O registers
SCIBaudRegVal
dc.w
52
; Initial SCI BAUD register value
EEBase
dc.w
$1000
; Base address of the on-chip EEPROM
EESize
dc.w
4096
; Size of the on-chip EEPROM
EEDelay
dc.w
_EEDELAY
; Address of EEPROM program/erase delay routine
AuxCmdCount
dc.w
0
; Number of commands in the auxiliary command table
AuxCmdTableP
dc.w
$0000
; Pointer to the auxiliary command table
D.2.3 Initial User CPU Register Values
The first seven fields in the
CustomData typedef struct
are used to
provide default values for the user CPU12 registers. The user CCR value is set
to 0x90. This sets the S bit, disabling the STOP instruction, and the I bit,
inhibiting IRQ interrupts. The X bit is cleared to allow the use of the XIRQ
interrupt as a programmer’s abort switch. The user SP value is set to 0x0a00,
which is one byte beyond the last on-chip RAM location available to the user.
The CPU12 stack pointer points to the last byte pushed onto the stack. All of the
other registers contain the value 0.
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
.
..
AR
CH
IVE
D B
Y F
RE
ES
CA
LE
SE
MI
CO
ND
UC
TO
R,
IN
C.