Freescale Semiconductor M68HC08AD, Справочное руководство

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M68HC08RG/AD
4 M68HC08 Family Reference Guide MOTOROLA
Memory and Addressing
M
= A memory location or absolute data, depending on addressing
mode
M:M + $0001
= A 16-bit value in two consecutive memory locations. The higher-
order (most significant) eight bits are located at the address of M,
and the lower-order (least significant) eight bits are located at the
next higher sequential address.
rel
= The relative offset, which is the two’s complement number stored
in the last byte of machine code corresponding to a branch
instruction
Condition Code Register (CCR) Bits
V
= Two’s complement overflow indicator, bit 7
H
= Half carry, bit 4
I
= Interrupt mask, bit 3
N
= Negative indicator, bit 2
Z
= Zero indicator, bit 1
C
= Carry/borrow, bit 0 (carry out of bit 7)
Bit Status BEFORE Execution of an Instruction (n = 7, 6, 5, ... 0)
(1)
1. For 2-byte operations such as LDHX, STHX, and CPHX, n = 15 refers to bit 15 of the
2-byte word or bit 7 of the most significant (first) byte.
Mn
= Bit n of memory location used in operation
An
= Bit n of accumulator
Hn
= Bit n of index register H
Xn
= Bit n of index register X
bn
= Bit n of the source operand (M, A, or X)
Bit Status AFTER Execution of an Instruction
(1)
1. For 2-byte operations such as LDHX, STHX, and CPHX, n = 15 refers to bit 15 of the
2-byte word or bit 7 of the most significant (first) byte.
Rn
= Bit n of the result of an operation (n = 7, 6, 5, … 0)
CCR Activity Figure Notation
– = Bit not affected
0 = Bit forced to 0
1 = Bit forced to 1
= Bit set or cleared according to results of operation
U = Undefined after the operation
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