Register Model
e200z3 Power Architecture Core Reference Manual, Rev. 2
Freescale Semiconductor
2-41
2.12.3.3
Debug Control Register 2 (DBCR2)
DBCR2, shown in
, is used to configure data address compare operations.
52–53
IAC4US
Instruction address compare 4 user/supervisor mode.
00 IAC4 debug events are not affected by MSR[PR].
01 Reserved.
10 IAC4 debug events can occur only if MSR[PR] = 0 (supervisor mode).
11 IAC4 debug events can occur only if MSR[PR] = 1 (user mode).
54–55
IAC4ER
Instruction address compare 4effective/real mode.
00 IAC4 debug events are based on effective address.
01 Unimplemented in the e200z3 (Book E real address compare), no match can occur.
10 IAC4 debug events are based on effective address and can occur only if MSR[IS] = 0.
11 IAC4 debug events are based on effective address and can occur only if MSR[IS] = 1.
56–57
IAC34M
Instruction address compare 3/4 mode.
00 Exact address compare. IAC3 debug events can occur only if the address of the instruction fetch is
equal to the value specified in IAC3. IAC4 debug events can occur only if the address of the instruction
fetch is equal to the value specified in IAC4.
01 Address bit match. IAC3 debug events can occur only if the address of the instruction fetch ANDed with
the contents of IAC4 is equal to the contents of IAC3, also ANDed with the contents of IAC4. IAC4 debug
events do not occur. IAC3US and IAC3ER settings are used.
10 Inclusive address range compare. IAC3 debug events can occur only if the address of the instruction
fetch is greater than or equal to the value specified in IAC3 and less than the value specified in IAC4.
IAC4 debug events do not occur. IAC3US and IAC3ER settings are used.
11 Exclusive address range compare. IAC3 debug events can occur only if the address of the instruction
fetch is less than the value specified in IAC3 or is greater than or equal to the value specified in IAC4.
IAC4 debug events do not occur. IAC3US and IAC3ER settings are used.
58–63
—
Reserved
32
33
34
35
36
37
38
39
40
41
42
43
44
63
Field DAC1US
DAC1ER
DAC2US
DAC2ER
DAC12M
DAC1LNK DAC2LNK
—
Reset
All zeros
1
1
Reset by processor reset
p_reset_b
if DBCR0[EDM]=0, as well as unconditionally by
m_por
. If DBCR0[EDM]=1,
DBERC0 masks off hardware-owned resources from reset by
p_reset_b
and only software-owned resources
indicated by DBERC0 will be reset by
p_reset_b
.
R/W
R/W
SPR
SPR 310
Figure 2-35. DBCR2 Register
Table 2-18. DBCR1 Field Descriptions (continued)
Bits
Name
Description
Содержание e200z3
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