Freescale Semiconductor e200z3, Справочное руководство

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Instruction Pipeline and Execution Timing
e200z3 Power Architecture Core Reference Manual, Rev. 2
6-10 Freescale Semiconductor
Figure 6-9. Basic Pipeline Flow, Branch Instructions
Figure 6-10 shows basic pipeline flow for branch speculation.
Figure 6-10. Basic Pipeline Flow, Branch Speculation
6.3.6 Basic Multi-Cycle Instruction Pipeline Operation
The divide instructions and the load and store multiple instructions require multiple cycles in the execute
stage.
Figure 6-11. Basic Pipeline Flow, Multi-Cycle Instructions
Instructions must complete and write back results in order. A single cycle instruction that follows a
multi-cycle instruction must wait for completion of the multi-cycle instruction prior to its writeback in
order to meet the in-order requirement. Result feed-forward paths are provided so that execution may
continue prior to result writeback.
6.3.7 Additional Examples of Instruction Pipeline Operation for Load and
Store
Figure 6-12 shows an example of pipelining two non–data-dependent load or store instructions with a
following data-dependent single-cycle instruction. While the first load or store begins accessing memory
DECODE EXEC
BR Inst.
Time Slot
Target Instruction EXEC WB
. . .
IFETCH Slot0
IFETCH DECODE
IFETCH DECODE Branch Instruction
Time Slot
Target Instruction
Slot0
DECODE EXEC
(Speculative Fetch)
BTB hit TFETCH Slot0
. . .
EXEC
IFETCH DECODE WB Load/Store Multiple Word/Divide Instruction
Time Slot
EXEC0 EXECn . . .