Freescale Semiconductor e200z3, Справочное руководство

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Instruction Pipeline and Execution Timing
e200z3 Power Architecture Core Reference Manual, Rev. 2
Freescale Semiconductor 6-11
in the MEM stage, the next load or store can be calculating a new EA in the DEC/EA stage. The add in
this example does not stall despite a data dependency on its preceding load instruction.
Figure 6-12. Pipelined Load/Store Instructions
For memory access instructions, wait states may occur. This causes a following memory access instruction
to stall since the following memory access may not be initiated as shown in
Figure 6-13 . Here, the first
ld/st instruction incurs a wait state on the bus interface, causing succeeding instructions to stall.
Figure 6-13. Pipelined Load/Store Instructions with Wait-State
6.3.8 Move to/from SPR Instruction Pipeline Operation
Most mtspr and mfspr instructions are treated like single-cycle instructions in the pipeline and do not
cause stalls. Exceptions are for the MSR, the debug SPRs, the embedded floating-point APUs, and MMU
SPRs, which do cause stalls.
Figure 6-14 through Figure 6-16 show examples of mtspr and mfspr
instruction timing.
Figure 6-14 applies to the debug SPRs and the EFPU’s EFSCR. These instructions do not begin execution
until all previous instructions have finished their execute stage. If a multicycle instruction precedes an
mfspr or mtspr instruction, the mfspr or mtspr instruction does not begin execution until the preceding
multicycle instruction moves into the writeback stage as shown in
Figure 6-14 . In addition, execution of
subsequent instructions stalls until the mfspr and mtspr instructions complete.
First Load/Store Instruction (No Wait)
Time Slot
Second Load/Store Instruction (No Wait)
Add Instruction
IFETCH WB DEC/EA
IFETCH MEM WB DEC/EA
WB IFETCH EXECUTE DEC
MEM
First Load/Store Instruction (With Wait)
Time Slot
Second Load/Store Instruction (No Wait)
Add Instruction
IFETCH Stall (wait) DEC/EA WB
IFETCH Stall MEM DEC / EA WB
EXECUTE IFETCH DEC Stall WB
MEM