Freescale Semiconductor DSPAUDIOEVM, Руководство пользователя

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DSPAUDIOEVM Users Guide, Rev. 2.4
This document contains information on a new product. Specifications and information herein are subject ot change without notice.
10 Freescale Semiconductor
Daughterboard Audio I / O and Clock Control Header
3.5.3 JP2 – Single/Double Speed Clocking Control
This jumper set controls whether or not the motherboard is in single or double speed mode. Position D forces the motherboard into double
speed mode. Position E allows the DSP GPIO pin PB11 to control the mode (e.g., through a PPP), and no jumper forces single speed mode.
An example of this signal’s use is for decoding of DTS 96/24 content. In this mode, it is required to update the masterclock ration expectation
in the D/A converters and S/PDIF transmitters because the DTS 96/24 decoder doubles the audio sample rate as part of the decoding process.
3.5.4 JP3 - FST_1 Connection
This set of jumpers determines which frame sync clock source is used for the AKM DAC4_6. The F position directs the ESAI_0 FST signal
to DAC4_6. Position G directs the ESAI_1 FST signal to DAC4_6, and population of both jumpers will synchronize/short the two ESAI port
FST lines.
NOTE
Position F should always be populated when using a 56362 or 56364 daughterboard.
3.5.5 JP4 – SCKT_1 Connection
This set of jumpers determines which serial clock source is used for the AKM DAC4_6. Position H directs the ESAI_0 SCKT signal to
DAC4_6, position I directs the ESAI_1 SCKT signal to DAC4_6 and population of both jumpers will synchronize/short the two ESAI port
SCKT lines.
NOTE
Position H should always be populated when using a 56362 or 56364 daughterboard.
3.5.6 JP5 - FSR_1 Connection
This jumper connects/shorts the FSR and FSR_1 signals together. No jumper means that the FSR_1 signal stops at the header.
3.5.7 JP6 - SCKR_1 Connection
This jumper connects/shorts the SCKR and SCKR_1 signals together. No jumper means that the SCKR_1 signal stops at the header.
3.5.8 JP7 - DSP MUTE Control
This jumper controls the mute signal when used in conjunction with the Software Architecture or GPIO control. With the jumper in place, the
mute control is connected to the DSP GPIO pin PB12. No jumper means that mute functionality will only be controlled by the motherboard.
3.5.9 JP8 - INT_0/SPDIF Error Flag Connection
This jumper connects the error flag signal from the AKM 4114 to the DSP GPIO pin PB15. This allows the DSP to be informed of the status
of the AKM 4114 S/PDIF receiver. If the connection is not desired this jumper can be removed.
3.5.10 JP9 - SDO5/SDI0 Configuration
This jumper set controls the signal connections of SDO5/SDI0. Depending on the ESAI setting in the DSP, this pin can be configured as an
input or an output. A jumper in position N feeds the SDI0 signal from the ADC2 microphone source. A jumper in the O position feeds the
SDO5 signal to DAC4_6.
3.5.11 JP10 SDO4/SDI1 Configuration
This jumper set controls the input source for SDI1. A jumper in the P position feeds the SDI1 signal from the AKM 4114 S/PDIF receiver. A
jumper in the Q position feeds the SDI1 signal from ADC1. There is no available jumper setting for use of the SDO4 signal.