28
3
► Execute Disable Bit
This item is used to enable/disable the Execute Disable Bit feature.
Intel's Execute Disable Bit functionality can help prevent certain classes of malicious buffer
overflow attacks when combined with a supporting operating system.
Execute Disable Bit allows the processor to classify areas in memory by where application
code can execute and where it cannot. When a malicious worm attempts to insert code in the
buffer, the processor disables code execution, preventing damage and worm propagation.
Replacing older computers with Execute Disable Bit-enabled systems can halt worm attacks,
reducing the need for virus-related repairs. By combining Execute Disable Bit with anti-virus,
firewall, spyware removal, e-mail filtering software, and other network security measures, IT
managers can free IT resources for other initiatives.
► Vander pool Technology
Intel® Vanderpool
Technology (i.e. Virtualization ) allows a platform to run multiple operating
systems and applications in independent partitions or “containers.” One physical compute
system can function as multiple “virtual” systems. Vanderpool Technology can help improve
future virtualizzation solutions. This item will be displayed only when the CPU supports this
feature and the setting is used to enable/disable it.
► Core Multi-Processing or Hyper-Threading Technology
It will be displayed single one at one time. It is used to enable or disable the feature and will be
displayed only if your CPU is supporting this feature.
Memory Timing Setting
► Memory Timing Setting
Select [Expert], you can configure the DRAM timing manually.
Select [Optimal], then system will use the DRAM timing provided by the memory vendor.
The provision of DRAM timing is done by a SPD device. The Serial Presence Detect (SPD)
device is a small EEPROM chip, mounted on a DDR2 memory module. It contains important
information about the module's speed, size, addressing mode and various other parameters,
Phoenix - AwardBIOS CMOS Setup Utility
Memory Timing Setting
Item Help
Memory Timing Setting
[
Optimal
]
Menu Level ►
x tCL (CAS# Latency)
Auto(0)
4
x tRCD
Auto(0)
4
Select [Expert] to
x tRP
Auto(0)
4
enter timings manually
x tRAS
Auto(0)
12
x Command Per Clock (CMD)
Auto(0T)
1T
** Advanced Memory Settings **
x tRRD
Auto(0)
2
x tRC
Auto(0)
16
x tWR
Auto(0)
4
x tWTR
Auto(0)
9
x tREF
Auto
7.8uS
↑↓→←:Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F7:Optimized Defaults
Optimal
