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Ganged refers to the use of both DRAM controllers within a memory controller acting in con-
cert to access memory. For a description of ganged (128-bit DRAM data width) and unganged
(64-bit DRAM data width) DRAM modes :
Ganged channels (DDR2) :
■
DCT channels A and B can be ganged as a single logical 128-bit DIMM.
■
Offers highest DDR2 bandwidth.
■
Requires both DIMMs in a logical pair to have identical size and timing parameters, both
DCTs programmed identically.
Unganged channels
■ DCT channels A and B operate as two completely independent 64-bit channels (both chan
-
nels operate at the same frequency).
■ Reduce DRAM page conflicts – more concurrent open dram pages .
■ Better bus efficiency.
Burst lengths supported
When both DCTs are enabled in unganged mode, BIOS must initialize the frequency of each
DCT in order.
► Power Down Enable
When power down mode is enabled, if all pages of the DRAMs associated with a CKE pin are
closed, then these parts are placed in power down mode.
► Power Down Mode
For non-mobile systems, power down mode should be set to [Channel] CKE control.
A DIMM or a group of DIMMs enters power down mode by deasserting the corresponding
clock enable signal when the DRAM controller detects that there are no transactions
scheduled to any of the DIMMs connected to the clock enable signal. A DIMM or a group of
DIMMs exits power down mode by asserting the corresponding clock enable signal when a
transaction is scheduled to any DIMM connected to the clock enable signal. There are two
CKE pins per DRAM channel. For each channel :
[Channel] CKE control. The DRAM channel is placed in power down when all chip selects
associated with the channel are idle.
[Chip Select] CKE control. A chip select or pair of chip selects is placed in power down
when no transactions are pending for the chip select(s).
► Auto Tweak Performance
Enables the DDR memory clocks to be tristated when alternate VID mode is enabled.
► DRAM Config_High Control
This item is used to set the memory configuration. Options are [Auto] and [Manual].
When select [Manual], the following two items will appear.
► DcqBypassMax
The DRAM controller arbiter normally allows transactions to pass other transactions in order to
optimize DRAM bandwidth. This field specifies the maximum number of times that the oldest
memory-access request in the DRAM controller queue may be bypassed before the arbiter
decision is overridden and the oldest memory-access request is serviced instead.
► FourActWindow
This item specifies the rolling tFAW window during which no more than 4 banks in a 8-bank
device are activated, per JEDEC DDR2 specification. For example, if this item is set to 10
clocks and an activate command is issued in clock N, then no more than three further activate
