3
36
Burst lengths supported
When both DCTs are enabled in unganged mode, BIOS must initialize the frequency of each
DCT in order.
► Power Down Enable
When power down mode is enabled, if all pages of the DRAMs associated with a CKE pin are
closed, then these parts are placed in power down mode.
► Power Down Mode
For non-mobile systems, power down mode should be set to [Channel] CKE control.
A DIMM or a group of DIMMs enters power down mode by deasserting the corresponding
clock enable signal when the DRAM controller detects that there are no transactions
scheduled to any of the DIMMs connected to the clock enable signal. A DIMM or a group of
DIMMs exits power down mode by asserting the corresponding clock enable signal when a
transaction is scheduled to any DIMM connected to the clock enable signal. There are two
CKE pins per DRAM channel. For each channel :
[Channel] CKE control. The DRAM channel is placed in power down when all chip selects
associated with the channel are idle.
[Chip Select] CKE control. A chip select or pair of chip selects is placed in power down
when no transactions are pending for the chip select(s).
DRAM Timing Configuration
► DRAM Timing Mode
When both DCTs (DRAM controller) are enabled in unganged mode, BIOS must initialize the
frequency of each DCT in order.
Settings are : [Auto]; [DCT 0]. (appear in AM2 CPU)
Settings are : [Auto]; [DCT 0]; [DCT1]; [Both]. (appear in AM2+ CPU)
► CAS Latency - tCL
The number of memory clocks it takes a DRAM to return data after the read CAS_L is asserted
depends on the memory clock frequency. The value that BIOS programs into the memory
CMOS Setup Utility - Copyright (C) 1985-2006, American Megatrends, Inc.
DRAM Timing Configuration
DRAM Timing Configuration
Help Item
DRAM Timing Mode
[Auto]
Auto
DCT0
↑↓←→:Move Enter:Select +/-/:Value F10:Save ESC:Exit F1:General Help
F9:Optimized Defaults
[Auto]
Options
