3
32
CKE pins per DRAM channel. For each channel :
[Channel] CKE control. The DRAM channel is placed in power down when all chip selects
associated with the channel are idle.
[Chip Select] CKE control. A chip select or pair of chip selects is placed in power down
when no transactions are pending for the chip select(s).
DRAM Timing Configuration
► Memory Speed Mode
This item is used to enable/disable provision of DRAM timing by SPD device. The Serial
Presence Detect (SPD) device is a small EEPROM chip, mounted on a DDR2 memory
module. It contains important information about the module's speed, size, addressing mode
and various other parameters, so that the motherboard memory controller (chipset) can better
access the memory device.
Select [Auto] for SPD enable mode.
Select [Limit], the DRAM speed will not exceed the specified value listed in the "Memory
Speed Adjust" item. If SPD value is faster than "Memory Speed Adjust" value, it will run at the
specified "Memory Speed Adjust" speed. Otherwise, SPD value is selected.
Select [Manual], then DRAM speed is manually selected according to the set value of
"Memory Speed Adjust".
► DRAM Timing Mode
When both DCTs (DRAM controller) are enabled in unganged mode, BIOS must initialize
the frequency of each DCT in order, you also can configure the timings manually.
Settings are : [Auto], [DCT 0], [DCT 1], [Both].
[DCT 1] and [Both] will appear only in AM2+ or AM3 CPU.
CMOS Setup Utility - Copyright (C) 1985-2006, American Megatrends, Inc.
DRAM Timing Configuration
DRAM Timing Configuration
Help Item
Memory Speed Mode
[Auto]
DRAM Timing Mode
[Auto]
Auto
Limit
Manual
↑↓←→:Move Enter:Select +/-/:Value F10:Save ESC:Exit F1:General Help
F9:Optimized Defaults
[Auto]
Options
