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CR300
57
• Pin Function
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Digital power supply
System reset. Rest when “L”
Mute input. Mute when “H”
Serial data input from CPU
Latch input from CPU
Serial data is latched at the falling edge.
Serial data transfer clock input from CPU
SENS output to CPU
CLock input for SENS serial-data readout
Input and output for unti-shock
WFCK output
XUGF output. MNT0 and RFCK output by
switching the command.
XPCK output. MNT1 output by switching the
command.
GFX output. MNT2 and XROF output by
switching the command.
C2PO output. MNT3 and GTOP output by
switching the command.
Outputs “H” when either subcode sync. S0 or S1 is
GFS is asmpled at 460Hz; when GFS is “H”, this pin
outputs “H”. If GFS is “L” eight consecutive samples,
this pint outputs “L”. Input when LKIN=“1”.
-
-
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-
-
-
EFM full-swing output (“L”=VSS, “H”=VDD)
Outputs “H” when the playback disc has emphasis,
and “L” when there is no emphasis.
Notes)
• PCMD is an MSB first, two's complement output.
• GTOP is used to monitor the frame sync protection status. (High: sync protection window released)
• XUGF is the negative pulse for the frame sync derived from the EFM signal. It is the signal before sync protection.
• XPCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge of XPCK and the EFM signal transition point coincide.
• GFS goes high when the frame sync and the insertion protection timing match.
• RFCK is derived with the crystal accuracy. This signal has a cycle of 136us.
• C2PO represents the data error status.
• XROF is generated when the 32K RAM exceeds the ±28 Frame jitter match.
Содержание CR300
Страница 33: ...CR300 33 Foil side ...
Страница 35: ...CR300 35 Foil side ...
Страница 60: ...CR300 60 7 2 DISPLAY FL TUBE PEL1097 FUNCTION PCB ASSY V701 Anode Grid Assignment 1 35 ...
Страница 61: ...CR300 61 Pin Assignment ...