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FIBOCOM L610 Series Hardware Guide
Page 35 of 59
Figure 3-8 Reset control timing
Note:
RESET_N is a sensitive signal, so it is recommended to add a debouncing capacitor close to the
module(<10nf). PCB layout should be far away from the RF interference and grounded, and avoid
routing on the edge and surface of PCB (to avoid module reset caused by ESD).
3.4 USB Interface
L610 modules support USB 2.0 and are compatible with USB High-Speed (480Mbits/s) and USB
Full-
Speed (12Mbits/s). Refer to “Universal Serial Bus Specification 2.0” for the timing and electrical
characteristics of L610 module USB bus.
3.4.1 USB Interface Definition
Pin Name
I/O
Pin
Description
USB_DM
I/O
70
USB differential data bus
USB_DP
I/O
69
USB differential data bus
USB_VBUS
PI
71
USB_DET
For more information about USB 2.0 specification, please visit
Note:
Since the module supports USB 2.0 High-Speed, TVS tube equivalent capacitance on the
USB_DM/DP differential signal cable is required to be less than 1pF, and a 0.5pF TVS is
recommended.
It is recommended to c
onnect a 0Ω resistor to USB_DM/DP differential line in series.
USB_DM and USB_DP are high-speed differential signal lines, which can achieve the maximum
transmission rate of 480Mbits/s and must follow the rules below in PCB Layout:
USB_DM and USB_DP signal lines control the differential impedance of 90
Ω
;
USB_DM and USB_DP signal lines shall be parallel and equal in length, and shall avoid
right-angle wiring;
USB_DM and USB_DP signal cables are routed on the signal layer closest to the ground layer,
and the lines shall be wrapped with GND.
VBUS needs an additional voltage between 3.4V and 5V. During USB operation, VBUS voltage
can not be less than 3.4V, otherwise port drop will occur.