Fastwel CPC507, Руководство пользователя

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CPC507
C P C 5 0 7 U s e r M a n u a l
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
PCI Express
The PCIe Gen3 bus is routed to the P15 XMC1 connector in accordance with the ANSI/VITA 42.3
standard. The interface enables you to connect XMC expansion modules with a set of links x1, x2,
x4, x8. A PCIe x4 link is routed to the P15 XMC2 connector. It can be used if the link on the XMC1
is narrowed down to x4.

PCI
The PCI bus is implemented on the Pericom PI7C9X130 reversible bridge chip connected to the
PCIe x2 bus. The following operating modes are supported: PCI 32bit/33MHz, PCI 64bit/66MHz.
The operation is supported both in the system and in the peripheral slot.

Audio
Support can be implemented via RIO (HD Audio Interface).

COM0
The debug COM port is routed to the IDC connector on the board.

LEDs
The LEDs for indication of startup diagnostics, drive activities, as well as User LEDs are routed to
the front panel. The diagnostics LED enables you to distinguish 4 board states: power OFF, power
ON, BIOS start, BIOS shutdown (operating system start). The drive activities LED informs about
the activities of the SATA interfaces. Two program-controlled LEDs are intended for user needs.

Watchdog
The module is equipped with a watchdog timer, which is built into the supervisor's microchip and
has a fixed actuation interval (1.6 s).

Power supply reset and monitoring
The CPU reset signal is generated from the following sources:

From the supervisor during power-up;

From the reset button;

From the watchdog timer;

From the Reset# signal of PCI bus (in the Slave mode).

Jumpers
The board has a switch for resetting BIOS settings to default settings.
3.2 Module Interfaces
3.2.1 PMC/XMC interface
The top side of the CPC507 board has connectors for PMC/XMC expansion modules, see
Figure 2-
2: Location of the main components of CPC507, top view
.
CPC507 supports two XMC/PMC modules:

PCI-X 64bit/66MHz bus is routed to P1-P4 PMC1 and PMC2 connectors (ANSI/VITA 39,
PCI-X for PMC and Processor PMC);

PMC I/O P4 is routed to RIO for the both mezzanines (PICMG PMC on CompactPCI R1.0
Specification).
PCIe x8 Gen3 bus is routed to the P15 XMC1 connector (ANSI/VITA 42.3, XMC: PCI Express
Protocol Layer), can be used in the x4 mode for two mezzanines.
.