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40
50
4
Frame Period in Pixel Clocks
54
4
Exposure Delay in Pixel Clocks
58
2
Serial Link Bit Period in Pixel Clocks
60
1
Camera Link Readout Mode
61
1
Camera Link Clock Frequency
62
1
Binning
63
1
Memory Options
64
1
Sensor Resolution - 8/10 bit
65
2
Trigger Mode (2nd Byte is Data FPGA dependent)
67
1
Frame count for Multi-Trigger mode
68
1
CC Mode: CC2, CC3, CC4 enable and edge select
69
59
Reserved for Control FPGA / base system
extension
128
2
Post-Trigger frame count (0 to 65535)
130
1
Debug Byte (for scoping Memory FPGA internal
signals)
131
1
Readback_count (1 to 255)
132
2
Vertical Blanking for USB “frame” (2 to 3613)
134
378
Available for Data FPGA functionality extensions
Table 4 - Camera State Memory Layout