Fastfame 3SLAV2, Руководство пользователя

Страница: 36 / 64

36
3SLAV2 User’s Manual
SDRAM Cycle Time Tras/Trc
Select the number of SCLKs for an access cycle.
The choice: 5/7, 6/8.
SDRAM RAS-to-CAS Delay
SDRAM RAS to CAS Delay is an important parameter that affects SDRAM
performance. If the system fails to boot up, please set this item to 3.
The Choice: 2, 3.
SDRAM RAS Precharge Time
The RAS Precharge means the timing to inactive RAS and the timing for
DRSM to do precharge before next RAS can be issued. RAS is the address
latch control signal of DRAM row address. The default setting is 3 clocks.
The choice: 2, 3.
System BIOS Cacheable
Select Enabled allows caching of the system BIOS ROM at F000h-FFFFFh,
resulting in better system performance. However, if any program writes to
this memory area, a system error may result.
The choice: Enabled, Disabled.
Video BIOS Cacheable
Select Enabled allows caching of the video BIOS, resulting in better system
performance. However, if any program writes to this memory area, a sys-
tem error may result
The choice: Enabled, Disabled.
Memory Hole At 15M-16M
You can reserve this area of system memory for ISA adapter ROM. When
this area is reserved, it cannot be cached. The user information of peripher-
als that need to use this area of system memory usually discusses their
memory requirements.
The choice: Enabled, Disabled.
CPU Latency Timer
The choice: Enabled, Disabled.
Delayed Transaction
The chipset has an embedded 32-bit posted write buffer to support delay
transactions cycles. Select Enabled to support compliance with PCI speci-